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我自己写的一个自动售货机的代码，但是quartus ii提示：
Warning (10199): Verilog HDL Case Statement warning at sellor.v(77): case item expression never matches the case expression，从s20开始的状态都没有出现，请问是怎么回事啊？不知道为什么不会出现s20及其以后的状态，求大神指点！
module sellor (
clk,coin_valid,din5,din10,din15,din20,din25,rst_n,
coin_accept,coin_enough,candy_out,dout
);
input wire clk;
input wire coin_valid,din5,din10,din15,din20,din25;
input wire rst_n;
output reg coin_accept,candy_out;
output reg [3:0]dout;
output reg coin_enough;
parameter s0 = 0000, s5 = 0001, s10 = 0011, s15 = 0010, s20 = 0110,
s25 = 0111,s30 = 0101, s35 = 0100, s40 = 1100,s45 = 1101;
reg [3:0]state;
always @(posedge clk or negedge rst_n)
if (!rst_n)
begin
state <= s0;
coin_enough <= 0;
coin_accept <= 0;
end
/*decide the state of the finite state machine*/
else if (coin_valid)
begin
case (state)
s0:
if (din5)//is it the priority decoder?? maybe using case is different;
state <= s5;
else if (din10)
state <= s10;
else if (din15)
state <= s15;
else if (din20)
state <= s20;
else if (din25)
state <= s25;
else
state <= s0;
s5:
if (din5)
state <= s10;
else if (din10)
state <= s15;
else if (din15)
state <= s20;
else if (din20)
state <= s25;
else if (din25)
state <= s30;
else
state <= s5;
s10:
if (din5)
state <= s15;
else if (din10)
state <= s20;
else if (din15)
state <= s25;
else if (din20)
state <= s30;
else if (din25)
state <= s35;
else
state <= s10;
s15:
if (din5)
state <= s20;
else if (din10)
state <= s25;
else if (din15)
state <= s30;
else if (din20)
state <= s35;
else if (din25)
state <= s40;
else
state <= s15;
s20:
if (din5)
state <= s25;
else if (din10)
state <= s30;
else if (din15)
state <= s35;
else if (din20)
state <= s40;
else if (din25)
state <= s45;
else
state <= s20;
default:
begin
state <= state;// can i express like this ??
coin_enough <= 1;
end
endcase
coin_accept <= 1;
end
else
state <= state;//the state of the fsm keep unchanged;
/*deal with the output candy_out of the machine*/
always @(state or rst_n) // is it neccessary to use a if sentence?
if (!rst_n)
begin
candy_out = 0;
dout = 4'b0000;
end
else
case (state)
s25:
begin
candy_out = 1;
dout = 4'b00_00;
state = s0;
end
s30:
begin
candy_out = 1;
dout = 4'b00_01;
state = s0;
end
s35:
begin
candy_out = 1;
dout = 4'b00_10;
state = s0;
end
s40:
begin
candy_out = 1;
dout = 4'b01_00;
state = s0;
end
s45:
begin
candy_out = 1;
dout = 4'b10_00;
state = s0;
end
default:
begin
candy_out = 0;
dout = 4'b00_00;
state = state;
end
endcase
endmodule |
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发表于 2012-11-21 11:58:34
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