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本帖最后由 唐龙 于 2012-7-3 17:00 编辑
[size=1.5em]DVT OVERVIEW
The Design and Verification Tools (DVT) platform is a powerful and modern, yet easy to use programming environment for the e language, SystemVerilog and VHDL. It enables faster and smarter code development and simplifies legacy code maintenance for novices and experts alike. Being created on the integrated development environment (IDE) concept, DVT is similar to well-known programming tools like Visual Studio and IntelliJ. An intuitive graphical user interface (GUI) integrates a smart code editor with a parser that runs in the background and a complete suite of tools for code navigation and debugging. In addition, the DVT IDE includes several domain-specific capabilities for design and verification, such as structural browsing of design entities, verification methodology support, and an innovative linting framework. |
More Snapshots of the DVT IDE
| [size=1.5em]FEATURES
- Built on the Eclipse platform for easy integration within a large plug-in ecosystem.
- Includes an IEEE standard compliant parser (IEEE 1800 SystemVerilog, IEEE 1647 e Language, and IEEE 1076 VHDL).
- Integrates with all major simulators to enable simplified simulation analysis.
- Works with revision control systems like CVS, Git, Subversion, ClearCase and bug tracking systems such as Bugzilla.
- Incorporates advanced editing features such as: syntax and semantic checks as you type, autocomplete, in-line reminders, code templates, macro expansion, code formatting, and refactoring for efficient code writting.
- Provides code and project navigation capabilities like hyperlinks, semantic search, class and structural browsing, and UML diagrams to simplify the maintenance of tens of thousands of code lines.
- Includes support for the Universal Verification Methodology (UVM), Open Verification Methodology (OVM), and Verification Methodology Manual (VMM) and UVM/OVM compliance checking capabilities.
Can anyone crack it, you may download it form http://www.dvteclipse.com/
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