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entity data_gen is
PORT( clk: in std_logic;
rst: in std_logic;
count ut integer range 0 to 255
);
end data_gen;
architecture Behavioral of data_gen is
begin
process(clk,rst)
variable counter:integer range 0 to 255;
begin
if (rst = '1') then
counter <= (others => '0');
else if (clk'event and clk = '1') then
if (counter=255) then
counter <= 0 ;
else
counter <= counter+1;
end if;
else
counter <= counter;
end if;
count <= counter;
end process;
end Behavioral; |
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