entity data_gen is
PORT( clk: in std_logic;
rst: in std_logic;
countut integer range 0 to 255
);
end data_gen;
architecture Behavioral of data_gen is
begin
process(clk,rst)
variable counter:integer range 0 to 255;
begin
if (rst = '1') then
counter <= (others => '0');
else if (clk'event and clk = '1') then
if (counter=255) then
counter <= 0 ;
else
counter <= counter+1;
end if;
else
counter <= counter;
end if;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity data_gen is
PORT( clk: in std_logic;
rst: in std_logic;
count : out integer
);
end data_gen;
architecture count_255 of data_gen is
begin
process(clk,rst)
variable counter:integer :=0 ;
begin
if (rst = '1') then
counter := 0;
else if (clk'event and clk = '1') then
if (counter = 255) then
counter := 0 ;
else
counter := counter+1;
end if;
else
counter := counter;
end if;
count <= counter;
end process;
end count_255;
我如果给PROCESS加上一个标号P1,进程结束 时end process p1;就会报两个错误, Syntax error near "process".Syntax error near "count_255".去掉进程的标号以后只有一个Syntax error near "process".
不知道是为什么总提示process的语法错误,求高人指点!