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Join DateFeb 2006Posts35Helped0 / 0Points1,286Level8
why DC compile this output as 0 module GF_matrix_dec(clk,re,address_read,data_out);
parameter address_width=8;
parameter data_width=8;
parameter num_words=256;
input clk,re;
input [address_width-1:0] address_read;
output [data_width-1:0] data_out;
reg [data_width-1:0] data_out;
reg [data_width-1:0] mem [0:num_words-1];
initial
begin
mem[ 0]<= 'b00000000;
mem[ 1]<= 'b00000001;
mem[ 2]<= 'b00000010;
mem[ 3]<= 'b00000100;
mem[ 4]<= 'b00001000
...............
..................
end
always @ (posedge(clk))
begin
if (re==1'b1)
begin
data_out <= mem[address_read];
end
end
endmodul
DC综合 data_out 为 8'h00. how to solve it, thanks |
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