新手求助陈版主:DC综合

shura_1206

我在DC综合时,有些警告不懂是怎么产生的,又怎么去解决呢?

脚本如下:
create_clock -name "CLKIN_in" [get_ports "CLKIN_in"] -period $CLKIN_PERIOD
create_generated_clock -name "clk_dly" -source CLKIN_in -divide_by 1 [get_pins "q_clk_gen/clk_dly"]
create_generated_clock -name "clkin_s" -source [get_pins "q_clk_gen/clk_dly"] -divide_by 1 [get_pins "q_clk_gen/clkin_s"]
set_clock_gating_check -setup 0.5 -hold 0.5 [all_clocks]
set_clock_latency 2 -source [get_clocks "*"]
set_clock_transition 1 [get_clocks "*"]
set_clock_uncertainty 1 [get_clocks "*"]
set_dont_touch_network [get_clocks *]

网表如下:
module clk_gen ( clkin, clk_osc, EN_DIGITAL, rf_clkpol, rf_clk_dly, clk_switch, mclk, en_digital_d );
  input clkin, clk_osc, EN_DIGITAL, rf_clkpol, rf_clk_dly, clk_switch;
  output mclk, en_digital_d;
  wire   clk_dly, en_digital_d1, n11, n14, n15, n1, n2, n3, n4;
  DLY3D1 dly_3ns_1_ ( .A(clkin), .Y(clk_dly) );
  DFFRQD4 en_digital_d1_reg ( .D(1'b1), .CK(clkin), .RB(n1), .Q(en_digital_d1) );
  DFFRQD4 en_digital_d_reg ( .D(en_digital_d1), .CK(clkin), .RB(n1), .Q(en_digital_d) );
  OAI22D2 u3 ( .A0(n11), .A1(n4), .B0(clk_switch), .B1(n14), .Y(mclk) );
  XNR2D2 u4 ( .A(rf_clkpol), .B(n15), .Y(n14) );
  BUFD3 u5 ( .A(n2), .Y(n1) );
  BUFD1 u6 ( .A(EN_DIGITAL), .Y(n2) );
  AOI22D4 u7 ( .A0(rf_clk_dly), .A1(clk_dly), .B0(clkin), .B1(n3), .Y(n15) );
  INVD2 u8 ( .A(rf_clk_dly), .Y(n3) );
  INVD1 u9 ( .A(clk_osc), .Y(n11) );
  INVD2 u10 ( .A(clk_switch), .Y(n4) );
endmodule

针对命令"set_clock_gating_check"有以下warning:
No controlling value could be found for the clock gating cell 'q_clk_gen/U3' for the clock pin 'B1'. (TIM-128)
Warning: No controlling value could be found for the clock gating cell 'q_clk_gen/U3' for the clock pin 'B1'. (TIM-128)
Warning: No controlling value could be found for the clock gating cell 'q_clk_gen/U4' for the clock pin 'B'. (TIM-128)
Warning: No controlling value could be found for the clock gating cell 'q_clk_gen/U7' for the clock pin 'A1'. (TIM-128)
Warning: Gated clock latch is not created for cell 'q_clk_gen/U7'on pin 'B0' in design '***_digital'. (TIM-141)
Warning: No controlling value could be found for the clock gating cell 'q_clk_gen/U7' for the clock pin 'A1'. (TIM-128)
Warning: Gated clock latch is not created for cell 'q_clk_gen/U3'on pin 'B1' in design ***_digital'. (TIM-141)
Warning: Gated clock latch is not created for cell 'q_clk_gen/U3'on pin 'A0' in design ***_digital'. (TIM-141)
Warning: Gated clock latch is not created for cell 'q_clk_gen/U7'on pin 'A1' in design ***_digital'. (TIM-141)
Warning: A non-unate path in clock network for clock 'CLKIN_in'
请问如何产生的?如何解决?

shura_1206

来人,帮帮忙呀

argintang

感覺是由於DC沒有發現控制CLOCK GATING的ENABLE信號.

jianchou1989

求解？？？？？？？？？？？？？

午后乐天派

解决了吗？

kevin9133023

建議到 DC or PT shell 下 man 這些 warning.
大致上,
TIM-128 是指你應該 set_case_analysis 在這些 clock gating cell 當 enable 的 pin 上一個 constant 值.
TIM-141 是指 clock gating cell 當 enable 的 pin 前面應當接一個 latch 才能算完整的 icg cell 結構, 如果你的 clock gating 電路只是要用單純的 and/or, 那就不用管這個 message.