Razavi: Monolithic Phase-Locked Loops and Clock Recovery Circuits 全部论文集

witten

Contents

PREFACE ix

Design of Monolithic Phase-Locked Loops and Clock Recovery Circuits-A Tutorial . . . . . . . . . . . . . . . . . . . . 1
B. Razavi (Original Paper).

PART 1 BASIC THEORY 41

Theory of AFC Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
W. J. Gruen (Proceedings of the IRE, August 1953).
Color-Carrier Reference Phase Synchronization Accuracy in NTSC Color Television . . . . . . . . . . . . . . . . . . . . 49
D. Richman (Proceedings of the IRE, January 1954).
Charge-Pump Phase-Locked Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
F. M. Gardner (IEEE Transuctions on Communications, November 1980).
z-Domain Model for Discrete-Time PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
J. P. Hein and J. W. Scott (IEEE Transactions on Circuits and Systems, November 1988).
Analyze PLLs with Discrete Time Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
J. Kovacs (Microwaves & RF: May 1991).
Properties of Frequency Difference Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
F. M. Gardner (IEEE Transactions on Communications, February 1985).
Frequency Detectors for PLLAcquisition in Timing and Carrier Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . 107
D. G. Messerschmitt (IEEE Transuctions on Communicutions, September 1979).
Analysis of Phase-Locked Timing Extraction Circuits for Pulse Code Transmission . . . . . . . . . . . . . . . . . . . . . 115
E. Roza (IEEE Transactions on Communicutions, September 1974).
Optimization of Phase-Locked Loop Performance in Data Recovery Systems . . . . . . . . . . . . . . . . . . . . . . . . . 129
R. S. Co and J. H. Mulligan, Jr. (IEEE Journal of Solid-State Circuits, September 1994).
Noise Properties of PLL Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
V. F. Kroupa (IEEE Transactions on Communications, October 1982).
PLLDLL System Noise Analysis for Low Jitter Clock Synthesizer Design . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1
B. Kim, T. C. Weigandt, and P. R. Gray (Proceedings of the International Symposium on Circ~litsa nd
Systems, June 1994).
Practical Approach Augurs PLL Noise in RF Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
M. O'Leary (Microwaves & RF: September 1987).
The Effects of Noise in Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
E. Hafner (Proceedings of the IEEE, February 1966)
A Simple Model of Feedback Oscillator Noise Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
D. B. Leeson (Proceedings of the IEEE, February 1966).
Noise in Relaxation Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
A. A. Abidi and R. G. Meyer (IEEE Journal of Solid-State Circuits, December 1983).
Analysis of Timing Jitter in CMOS Ring Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
T. C. Weigandt, B. Kim, and P. R. Gray (Proceedings of the Iizrernarional Symposium on Circuits and
Systems, June 1994).
Analysis, Modeling, and Simulation of Phase Noise in Monolithic Voltage-Controlled Oscillators . . . . . . . . . . . . . . 195
B. Razavi (Proceedings of the Custom Integrated Circuits Conference, May 1995).

PART 2 BUILDING BLOCKS 199

Start-up and Frequency Stability in High-Frequency Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
N. M. Nguyen and R. G. Meyer (IEEE Journal of Solid-State Circuits, May 1992).
MOS Oscillators with Multi-Decade Tuning Range and Gigahertz Maximum Speed . . . . . . . . . . . . . . . . . . . . . 2 11
M. Banu (IEEE Journal of Solid-State Circuits, April 1988).
A Bipolar 1 GHz Multi-Decade Monolithic Variable-Frequency Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9
J. T. Wu (International Solid-State Circuit Conference Digest of Technical Papers, February 1991).
A Digital Phase and Frequency Sensitive Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
J. I. Brown (Proceedings of the IEEE, April 197 1).
A 3-State Phase Detector Can Improve Your Next PLL Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
C. A. Sharpe (EDN Magazine, September 1976).
GaAs Monolithic PhaseRrequency Discriminator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
I. Shahriary et al. (IEEE Gallium Arsenide Integrated Circuits Symposium Digest of Technical
Papers, October 1985).
A New Phase-Locked Loop Timing Recovery Method for Digital Regenerators . . . . . . . . . . . . . . . . . . . . . . . 233
J. A. Bellisio (IEEE International Communications Conference Recording, June 1976).
A Phase-Locked Loop with Digital Frequency Comparator for Timing Signal Recovery . . . . . . . . . . . . . . . . . . . 237
J. A. Afonso, A. J. Quiterio, and D. S. Arantes (National Telecommunications Conference Recording, 1979).
Clock Recovery from Random Binary Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
J. D. H. Alexander (Electronics Letters, October 1975).
A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gbls . . . . . . . . . . . . . . . . . . . . . . . 244
A. Pottbacker, U. Langmann, and H. U. Schreiber (IEEE Journal of Solid-State Circuits,
December 1992).
A Self-correcting Clock Recovery Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
C. R. Hogge (IEEE Journal of Lightwave Technology, December 1985).

PART 3 MODELING AND SIMULATION 253

An Integrated PLL Clock Generator for 275 MHz Graphic Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
G. Gutierrez and D. DeSimone (Proceedings of the Custom Integrated Circuits Conference, May 1990).
The Macro Modeling of Phase-Locked Loops for the SPICE Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 59
M. Sitkowski (IEEE Circuits and Devices Magazine, March 1991).
Modeling and Simulation of an Analog Charge Pump Phase-Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . 264
S. Can and Y. E. Sahinkaya (Simulation, April 1988).
Mixed-Mode Simulation of Phase-Locked Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
B. A. A. Antao, F. M. El-Turky, and R. H. Leonowich (Proceedings of the Custom Integrated
Circuits Conference, May 1993).
Behavioral Represertstion for VCO and Detectors in Phase-Lock Systems . . . . . . . . . . . . . . . . . . . . . . . . . . 274
E. Liu and A. L. Sangiovanni-Vincentelli (Proceedings of the Custom Integrated Circuits
Conference, May 1992).
Behavioral Simulation Techniques for PhaseIDelay-Locked Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
A. Demir, E. Liu, and A. L. Sangiovanni-Vincentelli (Proceedings of the Custom Integrated Circuits
Conference, May 1994).

PART 4 PHASE-LOCKED LOOPS 283

A Monolithic Phase-Locked Loop with Detection Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
E. N. Murthi (IEEE Journal of Solid State Circuits, February 1979).
A 200-MHz CMOS Phase-Locked Loop with Dual Phase Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
K. M. Ware, H.-S. Lee, and C. G. Sodini (IEEE Journal of Solid-State Circuits, December 1989).
High-Frequency Phase-Locked Loops in Monolithic Bipolar Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
M. Soyuer and R. G. Meyer (IEEE Journal of Solid-State Circuits, June 1989).
A 6-GHz Integrated Phase-Locked Loop Using AlGaAsIGaAs Heterojunction Bipolar Transistors . . . . . . . . . . . . . . 3 10
A. W. Buchwald, et al. (IEEE Journal of Solid-State Circuits, December 1992).
A 6-GHz 60-mW BiCMOS Phase-Locked Loop with 2-V Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
B. Razavi and J. Sung (IEEE Journal of Solid-State Circuits, December 1994).
Design of PLL-Based Clock Generation Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
D. K. Jeong, et al. (IEEE Journal of Solid-State Circuits, April 1987).
A Variable Delay Line PLL for CPU-Coprocessor Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
M. G. Johnson and E. L. Hudson (IEEE Journal of Solid-State Circuits, October 1988).
A PLL Clock Generator with 5 to 11 0 MHz of Lock Range for Microprocessors . . . . . . . . . . . . . . . . . . . . . . . 339
I. A. Young, J. K. Greason, and K. L. Wong (IEEE Journal of Solid-State Circuits, November 1992).
A Wide-Bandwidth Low-Voltage PLL for PowerPC Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 47
J. Alvarez"", et al. (IEEE Journal of Solid-State Circuits, April 1995).
A 30-128 MHz Frequency Synthesizer Standard Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
R. F. Bitting and W. P. Repasky (Proceedings of the Custom Integrated Circuits Conference, May 1992).
Cell-Based Fully Integrated CMOS Frequency Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
D. Mijuskovic, et al. (IEEE Journal of Solid-State Circuits, March 1994).
Fully-Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and +SO psec Jitter . . . . . . . . . . . . 369
I. Novof, et al. (International Solid-State Circuit Conference Digest of Technical Papers, February 1995).
PLL Design for a 500 MBIs Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
M. Horowitz, et al. (International Solid-State Circuit Conference Digest of Technical Papers, February 1993).

PART 5 CLOCK AND DATA RECOVERY CIRCUITS 381

An Analog PLL-Based Clock and Data Recovery Circuit with High Input Jitter Tolerance . . . . . . . . . . . . . . . . . . 383
S. Y. Sun (IEEE Journal of Solid-State Circuits, April 1989).
A 30-MHz Hybrid AnalogDigital Clock Recovery Circuit in 2-ym CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . 389
B. Kim, D. N. Helman, and P. R. Gray (IEEE Journal of Solid-State Circuits, December 1990).
A BiCMOS PLL-Based Data Separator Circuit with High Stability and Accuracy . . . . . . . . . . . . . . . . . . . . . . 399
S. Miyazawa, et al. (IEEE Journal of Solid-State Circuits, February 1991).
A Versatile Clock Recovery Architecture and Monolithic Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
L. De Vito (Invited Paper).
A 155-MHz Clock Recovery Delay- and Phase-Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 1
T. H. Lee and J. F. Bulzacchelli (IEEE Journal of Solid-State Circuits, December 1992).
A Monolithic 156 Mbls Clock and Data Recovery PLL Circuit using the Sample-and-Hold Technique . . . . . . . . . . . 43 1
N. Ishihara and Y. Akazawa (IEEE Journal of Solid-State Circuits, December 1994).
A Monolithic 480 Mbls Parallel AGC/Decision/Clock Recovery Circuit in 1.2-ym CMOS . . . . . . . . . . . . . . . . . . 437
T. H. Hu and P. R. Gray (IEEE Journal of Solid-State Circuits, December 1993).
A Monolithic 622 Mblsec Clock Extraction and Data Retiming Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
B. Lai and R. C. Walker (International Solid-State Circuit Conference Digest of Technical Papers,
February 199 1).
A 660 Mbls CMOS Clock Recovery Circuit with Instantaneous Locking for NRZ Data and Burst-
Mode Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
M. Banu and A. Dunlop (International Solid-State Circuit Conference Digest of Technical Papers,
February 1993).
AMonolithic 2.3-Gbls 100-mW Clock and Data Recovery Circuit in Silicon Bipolar Technology . . . . . . . . . . . . . . 450
M. Soyuer (IEEE Journal of Solid-State Circuits, December 1993).
A 50 MHz Phase- and Frequency-Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
R. R. Cordell, et al. (IEEE Journal of Solid-State Circuits, December 1979).
NMOS ICs for Clock and Data Regeneration in Gigabit-per-Second Optical-Fiber Receivers . . . . . . . . . . . . . . . . 461
S. K. Enam and A. A. Abidi (IEEE Journal of Solid-State Circuits, December 1992).
A PLL-Based 2.5-Gbls Clock and Data Regenerator IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
H. Ransijn and P. O'Connor (IEEE Journal of Solid-State Circuits, October 1991).
A 2.5-Gblsec 15-mW BiCMOS Clock Recovery Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
B. Razavi and J. Sung (Symposium on VLSI Circuits Digest of Technical Papers, 1995).
An 8 GHz Silicon Bipolar Clock Recovery and Data Regenerator IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
A. Pottbacker and U. Langmann (IEEE Journal of Solid-State Circuits, December 1994).

witten

part 1

witten

part 2

witten

part 3

witten

part 4

witten

part 5

witten

part 7

witten

part 8

witten

part 6

witten

part 9