IEEE-A 40Gb Clock and Data Recovery Circuit in 0.18um CMOS(Razavi)

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER 2003

A 40Gb Clock and Data Recovery Circuit in 0.18um CMOS Technology

by
Jri Lee, Student Member, IEEE, and Behzad Razavi, Fellow, IEEE

Abstract—A phase-locked clock and data recovery circuit
incorporates a multiphase LC oscillator and a quarter-rate
bang-bang phase detector. The oscillator is based on differential
excitation of a closed-loop transmission line at evenly spaced
points, providing half-quadrature phases. The phase detector
employs eight flip-flops to sample the input every 12.5 ps, detecting
data transitions while retiming and demultiplexing the data into
four 10-Gb/s outputs. Fabricated in 0.18- m CMOS technology,
the circuit produces a clock jitter of 0.9 psrms and 9.67 pspp with
a PRBS of 2^31-1 while consuming 144 mW from a 2-V supply.
Index Terms—CDR circuits, demultiplexers, injection locking,
oscillators, phase detectors, phase-locked loops.

Index Terms  
CDR circuits, demultiplexers, injection locking,
oscillators, phase detectors, phase-locked loops.

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