1.2 – 1.5 + M instances flat design for 0.13um process

immonster

1.2 – 1.5 + M instances flat design for 0.13um process
ABSTRACT
This paper will highlight the benefits of using a flat design methodology for place and route. The technical challenges of a flat design methodology will be addressed on a 1.2 – 1.5 Million instances design in a .13um TSMC process. Using a flat design methodology might help to improve turn around time (TAT) and the quality of results (QOR) in the area of timing closure related to block sizing, cross-talk between blocks, and time budgeting in blocks. We will also provide statistics on CPU usage, and runtimes, on this particular size of design in a flat methodology as well as how JXT, PC, Astro and PT tools were utilized in a flat design.

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这么大的design flatten做啊，