overlap clock如何做ＣＴＳ

henry_wangjj

回复 7# 陈涛


    I've done CTS using the method given:
clk1, and clk2 have no sinks, and the clock tree is built rignt from mux/Y(in our design, clk1 comes from PAD, clk2 comes from and OSC), I do think the result is as expected, is this right?
besides, a Warning(there are multiple arcs between the input and output of the MUX)is issued since case_analysis on mux/S is removed, is this warning to be ignored?

thanks in advance.

henry_wangjj

and one more question,
during synthesis, I think there's no need to do incremental mapping for clk1(or clk2).
Using clk1(or clk2) as the clock source with the proper set_case_analysis is fine since clk1&clk2 are the same to synthesis
yeah?

herrzhou

mark下，没明白

fangwang85

回复 9# tianxiong_14


   那么可以先长mux Y端后的，然后设置成dont touch 应该也是可以的。我不太理解你说的3个clock设置成一样 是什么意思，是creat clock的定义吗？dc阶段还是icc啊

fangwang85

tianxiong_14 发表于 2011-8-24 13:05
回复 8# henry_wangjj

请教下， clock1 和clock2 没有必要做balance ，为何还要放在一个group中啊