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发表于 2012-11-18 17:39:21
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probably, you make a mistake on ESL processor design tools like processor designer from synopsys. you should focus on their ability of describing and implementing your idea, namely, the description ability of its built-in modeling language, the ability of the associated facilities like software tool chain to make the behavior of described processor models consistent to what you expected.
as to the efficiency of the generated RTL code, you should not concern so much. because it is not a hard work to optimize the generated rtl code for an asic designer who is familiar with verilog and asic design, when the pipeline of your processor already established.
according to my experience, I spend 3 months to determine the ISA of the processor, describe the processor's lisa model, customize the c compiler, and simulate the generated rtl code (to prove the behavior of the rtl code is consistent to the lisa model).
but only 2 weeks to optimize the generated rtl code to shrink the area of the processor to only 1/4 of that of original generated rtl code. |
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