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发表于 2011-6-7 21:52:50
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显示全部楼层
module modula
(
clk,
rst,
din,
dout
);
input clk;
input rst;
input din;
output dout;
reg dout;
reg [1:0] q;
reg [1:0] x;
reg [1:0] y;
reg [3:0] f;
always@(posedge clk)
begin
if(rst==1)
begin
q <= 2'd0;
x <= 2'd0;
f <= 4'd0;
x <= 2'd0;
end
else
begin
case(q)
0:
begin
q <= 2'd1;
f[1] <= 1'b1;
f[3] <= 1'b0;
x[1] <= din;
y <= x;
end
1:
begin
q <= 2'd2;
f[0] <= 1'b1;
f[2] <= 1'b0;
end
2:
begin
q <= 2'd3;
f[1] <= 1'b0;
f[3] <= 1'b1;
x[0] <= din;
end
3:
begin
q <= 2'd0;
f[0] <= 1'b0;
f[2] <= 1'b1;
end
endcase
end
end
always@(*)
begin
case(y)
2'b00:dout = f[0];
2'b01:dout = f[1];
2'b10:dout = f[3];
default:dout = f[2];
endcase
end
endmodule |
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