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发表于 2011-3-15 13:33:08
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本帖最后由 fhchen2002 于 2011-3-15 13:37 编辑
The address and command decoders are too simple in EEPROM,
and the row and column decoders are too regular, that IC (silicon) design does not benefit much from logic design flow.
After the logic synthesis, it would be automatic placement of cells and auto-route.
The area utilization efficiency in general (of such design flow) is relatively low, compared to fully customized layout and manual route. If the cells are too regular, silicon design does not benefit from APR (Auto Place-&-Route) flow.
EEPROM, like other memory ICs, does not use the same amount of metal layers as logic ICs usually do.
This is another reason why EEPROM design does not benefit from logic synthesis then APR flow.
Please be aware that I am not saying you CAN'T use logic design flow to implement the aforementioned parts in the EEPROM. I simply say there's not much benefit doing so.
Therefore people wouldn't do things that way.
The short answer is EEPROM IC design uses fully customized circuit design flow. |
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