用VHDL这样描述可否:
process(rst,clk,req)
begin
if(rst = '1') then
cs <= "000";
elsif(posedge(clk)) then
case cs is
when "000" =>
if(req = '1') then -- startup
cntr <= 0x300;
---- and output
cs <= "001";
else
cntr <= 0x000;
cs <= "000";
end if;
when "001" =>
if(req = '1')
cntr <= cntr - 1;
if(cntr = 0x200) then
cs <= "010";
---- and output
else
cs <= "001";
end if;
end if;
when "010" =>
........