Hardware Acceleration of EDA Algorithms

notfackerd · 发表于 2011-1-24 15:25:17

马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。

您需要登录才可以下载或查看，没有账号？注册

x

Hardware Acceleration of EDA Algorithms.jpg

Kanupriya Gulati · Sunil P. Khatri
Hardware Acceleration
of EDA Algorithms
Custom ICs, FPGAs and GPUs

Preface
In recent times, serial software applications have no longer enjoyed significant
gains in performance with process scaling, since microprocessor performance gains
have been hampered due to increases in power and manufacturability issues, which
accompany scaling. With the continuous growth of IC design complexities, this
problem is particularly significant for EDA applications. In this research monograph,
we evaluate the feasibility of hardware platforms such as custom ICs, FPGAs,
and graphics processors, for accelerating EDA algorithms. We choose applications
which contribute significantly to the total runtime of the VLSI design flow and
which have varied degrees of inherent parallelism in them. We study the acceleration
of such algorithms on these alternative platforms. We also present an automated
approach to accelerate certain specific types of uniprocessor subroutines on
the GPU.
This research monograph consists of four parts. The alternative hardware platforms,
along with the details of the programming model used for interfacing with
the graphics processing units, are discussed in the first part of this monograph.
The second part of this monograph studies the acceleration of an algorithm in
the control-dominated category, namely Boolean satisfiability (SAT). The third part
studies the acceleration of some algorithms in the control plus data parallel category,
namely Monte Carlo based statistical static timing analysis, circuit simulation,
fault simulation and fault table generation. In the fourth part of the monograph, we
present the automated approach to generate GPU code to accelerate certain software
subroutines.

Hardware Acceleration of EDA Algorithms.pdf