Measuring the Gap Between FPGAs and ASICs

yjz888

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2011-1-19 17:31 上传

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Abstract—This paper presents experimental measurements of
the differences between a 90-nm CMOS field programmable
gate array (FPGA) and 90-nm CMOS standard-cell applicationspecific
integrated circuits (ASICs) in terms of logic density, circuit
speed, and power consumption for core logic. We are motivated
to make these measurements to enable system designers to make
better informed choices between these two media and to give
insight to FPGA makers on the deficiencies to attack and, thereby,
improve FPGAs. We describe the methodology by which the measurements
were obtained and show that, for circuits containing
only look-up table-based logic and flip-flops, the ratio of silicon
area required to implement them in FPGAs and ASICs is on
average 35. Modern FPGAs also contain “hard” blocks such as
multiplier/accumulators and block memories. We find that these
blocks reduce this average area gap significantly to as little as 18
for our benchmarks, and we estimate that extensive use of these
hard blocks could potentially lower the gap to below five. The ratio
of critical-path delay, from FPGA to ASIC, is roughly three to four
with less influence from block memory and hard multipliers. The
dynamic power consumption ratio is approximately 14 times and,
with hard blocks, this gap generally becomes smaller

yjz888

加附件  Index Terms—Application-specific integrated circuits (ASIC),
area comparison, delay comparison, field programmable gate array
(FPGA), power comparison.

lujunfeng111

好像只是一篇论文，如果是书就好了。