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Report : area
Design : ramp_curveN_dc
Version: I-2013.12-SP5-6
Date : Fri Jan 22 10:56:16 2016
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Information: Updating design information... (UID-85)
Library(s) Used:
xxxxxx
Number of ports: 61
Number of nets: 586
Number of cells: 490
Number of combinational cells: 347
Number of sequential cells: 143
Number of macros/black boxes: 0
Number of buf/inv: 56
Number of references: 68
Combinational area: 762.048007
Buf/Inv area: 41.865601
Noncombinational area: 860.126386
Macro/Black Box area: 0.000000
Net Interconnect area: undefined (Wire load has zero net area)
Total cell area: 1622.174394
Total area: undefined
上面是我用dc跑出的一个面积报表
大家是怎么理解这些术语的
以下是我的理解
Number of ports: 61 i/o bit 数
Number of nets: 586 ??
Number of cells: 490 总的逻辑单元(是与非,或非门吗?)
Number of combinational cells: 347 组合逻辑
Number of sequential cells: 143 时序逻辑
Number of macros/black boxes: 0 宏/黑盒子?
Number of buf/inv: 56 ??
Number of references: 68 ??
Combinational area: 762.048007 组合逻辑面积
Buf/Inv area: 41.865601
Noncombinational area: 860.126386 非组合逻辑面积(是指时序逻辑吗?)
Macro/Black Box area: 0.000000
Net Interconnect area: undefined (Wire load has zero net area)
Total cell area: 1622.174394
Total area: undefined