ADC S/H amplifier 问题。急求。

zhuxuxiaojie · 发表于 2011-1-11 15:56:18

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设计了个S/H(fiip-around) 的放大器 (gain=82db)，用理想的switch仿真SFDR，低频下SFDR有92db，但是高频200M输入下就变成了71db，按道理用的是理想的开关采样电路，SFDR不应该随输入频率发生这么大的变化，如果说我设计的运放有问题，那么低频下线性度不可能有92db，所以现在有些矛盾了，不知道问题出在哪里，求高人指点。

fhchen2002 · 发表于 2011-1-11 16:07:40

回复 1# zhuxuxiaojie

也可能是你的 OpAmp 設計造成的
Your OpAmp is supposed to settle to the required accuracy level before the end of each sample.

T_settle < 0.5 / F_sample

At low sampling freuquency, your OpAmp has long enough settling time.
At high frequency, your OpAmp may not have enough settling time.

To verify whether your OpAmp bandwidth / settling is the dominant factor, replace your OpAmp with an ideal OpAmp and conduct the S/H simulation again.

fhchen2002 · 发表于 2011-1-11 16:10:06

If you are talking about F_in (low frequency vs. 200 MHz), it would be similar issue.
Still OpAmp could be the dominant factor.

zhuxuxiaojie · 发表于 2011-1-11 16:24:22

回复 3# fhchen2002

谢谢，我之前用过ideal amp 仿真，结果是好的，我设计的amp，bandwidth=1G，sample frequence=100M，slew rate什么的都没问题，Tsettle=1.5ns，而且运放只是工作在hold状态下，对于运放来说201M input signal is the same as 1M input. 而且我试过将运放gain提高到140db，SFDR在200M input signal下就有93db。但是这个还是无法解释gain=82db时候，低频输入下好，高频输入下不好。还是存在矛盾。

zhuxuxiaojie · 发表于 2011-1-11 16:26:27

回复 4# zhuxuxiaojie

不好意思， Tsettle是3ns。

fhchen2002 · 发表于 2011-1-11 16:54:02

本帖最后由 fhchen2002 于 2011-1-11 17:10 编辑

May I know when you wrote

t_settle = 3 ns

To what accuracy level did you refer to?
For instance, (compared to steady state, i.e., the voltage level when t = infinity) the OpAmp settles to |V_infinity - V(3 ns after clock edge)| < 0.1%, ...

Assuming simple single-pole model,
Unity-gain bandwidth = 1 GHz
At F_in = 200 MHz, your OpAmp has open-loop gain about 5 only (in this order of magnitude).
You won't have good enough accuracy when you close the loop
-> your close-loop transfer function = (A_v(f)) / [1 + A_v(f)] (not close enough to 1).

Still bandwidth issue.