ieee paper

shaweikang1984

Exploring Area and Delay Tradeoffs in FPGAs With Architecture and Automated Transistor Design

Abstract—Field-programmable gate arrays (FPGAs) are used
in a variety of markets that have differing cost, performance and
power consumption requirements. While it would be ideal to serve
all these markets with a single FPGA family, the diversity in the
needs of these markets means that generally more than one family
is appropriate. Consequently, FPGA vendors have moved to provide
a diverse set of families that sit at different points in the areaspeed-
power design space.
This paper aims to understand the circuit and architectural design
attributes of FPGAs that enable tradeoffs between area and
speed, and to determine the magnitude of the possible tradeoffs.
This will be useful for architects seeking to determine the number
of device families in a suite of offerings, as well as the changes to
make between families.
We explore a broad range of architectures and circuit designs
and developed a transistor sizing tool that automatically optimizes
each design. In this paper, we describe this tool and demonstrate
that it achieves results that are comparable to past work but with
vastly less effort.
We then use the designs produced by the tool to explore the range
of tradeoffs possible. We find that through architecture and transistor
sizing changes it is possible to usefully vary the area of an
FPGA by a factor of 2.0 and the performance of an FPGA by a
factor of 2.1. We also observe that the range of area and delay
tradeoffs possible by varying only the transistor sizing of a single
architecture is larger than the ranges observed in past architectural
experiments. In addition to transistor size, we note that LUT
size is one of the most useful parameters for trading off area and
delay.

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dongdong13

不错，再来一点啊

shaweikang1984

??

zm218wri

thanks  a  lot!