Low Voltage CMOS Delta Sigma Modulators

hi_china59

CHAPTER 1 INTRODUCTION......................................................................................... 1
1.1 MOTIVATION..................................................................................................................... 1
1.2 ORGANIZATION................................................................................................................ 2

CHAPTER 2 FUNDAMENTALS OF ΔΣ MODULATORS ............................................. 5
2.1 INTRODUCTION ................................................................................................................... 5
2.2 QUANTIZATION................................................................................................................... 6
2.2.1 QUANTIZATION ERROR ..................................................................................................... 7
2.2.2 PERFORMANCE METRICS ................................................................................................ 10
2.2.2.1 Resolution.................................................................................................................... 10
2.2.2.2 Signal-to-Noise Ratio (SNR)....................................................................................... 11
2.2.2.3 Signal-to-Noise plus Distortion Ratio (SNDR) ........................................................... 11
2.2.2.4 Dynamic Range ........................................................................................................... 11
2.2.3 SINGLE-BIT QUANTIZATION ............................................................................................ 12
2.2.4MULTI-BIT QUANTIZATION.............................................................................................. 13
2.3 OVERSAMPLING TECHNIQUE ........................................................................................... 14
2.3.1 NYQUIST-RATE A/D CONVERTERS................................................................................... 15
2.3.2ADVANTAGE OF OVERSAMPLING TECHNIQUE ................................................................ 15
2.3.3 QUANTIZATION NOISE MODEL........................................................................................ 17
2.4 NOISE-SHAPED ΔΣ MODULATOR .................................................................................... 17
2.4.1 FIRST-ORDER NOISE-SHAPING........................................................................................ 19
2.4.2 SECOND-ORDER NOISE-SHAPING ................................................................................... 22
2.4.3 HIGHER-ORDER NOISE-SHAPING.................................................................................... 24
2.4.3.1 Single-Loop Topology ................................................................................................. 25
2.4.3.2 Cascade Topology........................................................................................................ 26
2.5 MULTIBIT QUANTIZATION ΔΣ MODULATOR..................................................................... 27
2.6 BANDPASS ΔΣ MODULATOR............................................................................................ 28
2.7 SUMMARY ......................................................................................................................... 28

CHAPTER 3 THE DESIGN OF LOW VOLTAGE SWITCHED-CAPACITOR
CIRCUITS FOR ΔΣ MODULATORS................................................................................. 29
3.1 INTRODUCTION ..................................................................................................................29
3.2 SWITCHED-CAPACITOR CIRCUITS....................................................................................30
3.3 LOW VOLTAGE SWITCHED-CAPACITOR CIRCUITS ..........................................................31
3.3.1 VOLTAGE BOOSTING TECHNIQUE ....................................................................................33
3.3.2MULTI-THRESHOLD VOLTAGE PROCESS ..........................................................................34
3.3.3 BOOTSTRAPPED SWITCH..................................................................................................35
3.3.3 BOOTSTRAPPED SWITCH AS A SAMPLING SWITCH ..........................................................36
3.4 THE ORIGINAL SWITCHED OPAMP PRINCIPLE ................................................................38
3.5 FULLY DIFFERENTIAL SWITCHED OPAMP WITH DOUBLED OUTPUT ..............................42
3.5.1 FULLY DIFFERENTIAL SWITCHED OPAMP ........................................................................42
3.5.2 COMMON MODE FEEDBACK (CMFB) .............................................................................44
3.5.4 SIMULATION RESULTS......................................................................................................46
3.6 LOW VOLTAGE QUANTIZER ..............................................................................................49
3.6.1 LOW VOLTAGE COMPARATOR..........................................................................................49
3.6.2 LOW VOLTAGE QUANTIZER .............................................................................................50
3.7 SUMMARY ..........................................................................................................................51

CHAPTER 4 THE LOW VOLTAGE NESTED-CHOPPER ΔΣ MODULATOR.........53
4.1 INTRODUCTION ..................................................................................................................53
4.2 NOISE CONSIDERATION ....................................................................................................53
4.2.1AUTOZEROING AND CORRELATED DOUBLE SAMPLING (CDS)........................................54
4.2.2 CHOPPER STABILIZED SCHEME........................................................................................55
4.2.3 RESIDUAL NOISE AND NESTED-CHOPPER AMPLIFIER .....................................................56
4.3 CHOPPER-STABILIZED ΔΣ MODULATOR..........................................................................58
4.4 NESTED-CHOPPER ΔΣ MODULATOR................................................................................60
4.4.1 CONSIDERATION ..............................................................................................................60
4.4.2 NESTED-CHOPPER IN ΔΣMODULATOR............................................................................61
4.5 SYSTEM CONSIDERATION.................................................................................................63
4.5.1 A Second-Order ΔΣ Modulator .......................................................................................63
4.5.2 A Highpass Second-Order ΔΣ Modulator........................................................................64
4.5.3 The First Stage.................................................................................................................65
4.5.4 The Second Stage ............................................................................................................67
4.5.5 Comparator.....................................................................................................................70
4.6 NOISE ANALYSIS ...............................................................................................................70
4.6.1 The First Stage.................................................................................................................70
4.6.2 Jitter Noise.......................................................................................................................75
4.7 SIMULATION......................................................................................................................75
4.7.1 The Finite Gain of the Opamp ........................................................................................ 76
4.7.2 MATLAB Simulation ..................................................................................................... 77
4.7.3 HSPICE Simulation........................................................................................................ 79
4.8 EXPERIMENTAL RESULTS ................................................................................................ 80
4.8.1 Input Signal Source and Input Termination Circuit........................................................ 81
4.8.2 Power Supply and Ground.............................................................................................. 81
4.8.3 Reference Voltage Generator .......................................................................................... 82
4.8.4 Layout and Pin Assignment ............................................................................................ 84
4.8.5 Measurement Results...................................................................................................... 85
4.9 SUMMARY ......................................................................................................................... 89

CHAPTER 5 A LOW-VOLTAGE SECOND-ORDER ΔΣ MODULATOR USING
SINGLE OPAMP................................................................................................................... 91
5.1 INTRODUCTION ................................................................................................................. 91
5.2 SYSTEM CONSIDERATIONS.............................................................................................. 91
5.3 IMPLEMENTATION.............................................................................................................. 94
5.3.1 INTEGRATOR.................................................................................................................... 94
5.3.2 QUANTIZER ..................................................................................................................... 98
5.3.3MULTIPLEXER ................................................................................................................. 98
5.3.4 DAC FEEDBACK ............................................................................................................. 99
5.3.5ASECOND-ORDER INTEGRATOR WITH DAC FEEDBACK .............................................. 100
5.4 CLOCK GENERATOR....................................................................................................... 100
5.5 SIMULATION RESULTS.................................................................................................... 101
5.6 EXPERIMENTAL RESULTS .............................................................................................. 104
5.7 SUMMARY ....................................................................................................................... 107

CHAPTER 6 A LOW-VOLTAGE FOURTH-ORDER BANDPASS ΔΣ MODULATOR
.............................................................................................................................................. 109
6.1 INTRODUCTION ............................................................................................................... 109
6.2 SYSTEM CONSIDERATION ...............................................................................................111
6.2.1 The Sampling Frequency.............................................................................................. 113
6.3 IMPLEMENTATION.............................................................................................................114
6.3.1 The First Resonator....................................................................................................... 115
6.3.2 The Second Resonator .................................................................................................. 119
6.3.3 Quantizers..................................................................................................................... 122
6.3.4 The Multiplexers........................................................................................................... 123
6.4 SIMULATION.....................................................................................................................123
6.5 EXPERIMENTAL RESULTS ...............................................................................................126
6.5.1 Input Termination Circuit ..............................................................................................127
6.5.2 Layout and Pin Assignment...........................................................................................127
6.5.3 Measurement Results ....................................................................................................128
6.6 SUMMARY ........................................................................................................................131

CHAPTER 7 CONCLUSIONS........................................................................................133
7.1 CONCLUSIONS.................................................................................................................133
7.2 RECOMMENDATIONS FOR FUTURE WORKS...................................................................134

APPENDIX ...........................................................................................................................135
A.1 INTRODUCTION................................................................................................................135
A.2 CONSIDERATIONS OF THE DESIGN ................................................................................136
A. NONLINEAR ERROR OF THE DAC.......................................................................................136
B. FOUR POINTER DWA(FPDWA).........................................................................................136
A.3 BEHAVIORAL SIMULATION..............................................................................................139
A.4 CIRCUIT IMPLEMENTATION.............................................................................................140
A. SECOND-ORDER DELTA-SIGMA MODULATOR WITH NINE-LEVEL QUANTIZATION ...............140
B. DIGITAL-ANALOG CONVERTER (DAC)..............................................................................146
A.5 CONCLUSIONS ................................................................................................................149

mtwumtwu

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risccpu

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