modelsim仿真的问题

lq4080 · 发表于 2010-11-3 11:14:21

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我编写了一个很小的文件，用modelsim仿真，发现输出始终为0，不知道为什么？代码如下：
被仿真代码：
module Devider(
clkout,
clkin,
fast,
slow
);
input clkin;
input fast;
input slow;
output clkout;
reg  clkout;
reg  [3:0] counter;
always @(posedge clkin)
begin
if(fast == 1)
  counter <= counter + 2;
  else
if(slow == 1)
   counter <= counter;
   else
   counter <= counter + 1;
if(counter <= 4)
  clkout <= 1;
  else
clkout <= 0;
end
endmodule

testbench：
`timescale 100ns/10ns
//`include "Devider.v"
module T_Devider;
  reg clkin;
  reg fast;
  reg slow;
  wire clkout;

  Devider dev(clkout,clkin,fast,slow);

  initial
begin
   clkin = 0;
   forever #0.5 clkin = ~clkin;
end

//  Devider dev(clkout,clkin,fast,slow);

//  always #0.5 clkin = ~clkin;
  initial
begin
   fast = 0;
   slow = 0;
   #800 fast = 1;
   #100 fast = 0;
   #1000 slow = 1;
   #100 slow = 0;
end
  initial
  begin
$monitor($time,,,clkin,,,fast,,,slow,,,clkout);
#10000 $stop;
  end
endmodule

望高手帮帮忙看看，谢谢！