时序分析的圣经

chasing

这本书详细介绍了时序分析方法，被誉为时序分析的圣经，是国外许多高校的必修课程。

eetop.cn_Timing (2010 chasing).part1.rar (4 MB, 下载次数: 3064 )

2010-10-30 10:10 上传

点击文件名下载附件

eetop.cn_Timing (2010 chasing).part2.rar (1.28 MB, 下载次数: 2780 )

2010-10-30 10:11 上传

点击文件名下载附件

1. PREDUCTION/INTROFACE

2. A QUICK OVERVIEW OF CIRCUIT SIMULATION
Introduction
Formulation of circuit equations
Examples of equation formulation by inspection
Solution of nonlinear equations
Solution of differential equations
Putting it all together
A primer on solving systems of linear equations
Summary

3. FREQUENCY-DOMAIN ANALYSIS OF LINEAR SYSTEMS
Introduction
Interconnect modeling
Typical interconnect structures
The Elmore delay metric
Asymptotic waveform evaluation
Krylov subspace-based methods
Fast delay metrics
Realizable circuit reduction
Summary

4. TIMING ANALYSIS FOR A COMBINATIONAL STAGE
Introduction
Identifying a logic stage
Delay calculation under purely capacitive loads
Effective capacitance: Delays under RC loads
Capacitive coupling effects
Summary
viii TIMING

5. TIMING ANALYSIS FOR COMBINATIONAL CIRCUITS
Introduction
Representation of combinational and sequential circuits
False paths
Finding the most critical paths
Summary

6. STATISTICAL STATIC TIMING ANALYSIS
Modeling parameter variations
Early work on statistical STA
Statistical STA in the absence of spatial correlation
Statistical STA under spatial correlations
Summary
7. TIMING ANALYSIS FOR SEQUENTIAL CIRCUITS
Introduction
Modeling parameter variations
Early work on statistical STA
Statistical STA in the absence of spatial correlation
Statistical STA under spatial correlations
Summary
Introduction
Clocking disciplines: Edge-triggered circuits
Clocking disciplines: Level-clocked circuits
Clock schedule optimization for level-clocked circuits
Timing analysis of domino logic
Summary

8. TRANSISTOR-LEVEL COMBINATIONAL TIMING OPTIMIZATION
Introduction
Transistor sizing
The TILOS algorithm
Transistor sizing using convex programming
Lagrangian multiplier approaches
Timing budget based optimization
Generalized posynomial delay models for transistor sizing
Dual optimization
Resolving short path violations
Summary

9. CLOCKING AND CLOCK SKEW OPTIMIZATION
Accidental and deliberate clock skew
Clock network construction
Clock skew optimization
Clock skew optimization with transistor sizing
Timing analysis of sequential circuits for skew scheduling
Wave pipelining issues
Deliberate skews for peak current reduction
Summary

10. RETIMING
Contents ix
Introduction to retiming
A broad overview of research on retiming
Modeling and assumptions for retiming
Minimum period optimization of edge-triggered circuits
Minimum area retiming of edge-triggered circuits
Minimum period retiming of level-clocked circuits
Minimum area retiming of level-clocked circuits
Summary

11. CONCLUSION
Appendices
A–Closed-form formulæ for the roots of cubic and quartic equations
A.1
A.2
Cubic equations
Quartic equations
B–A Gaussian approximation of the PDF of the maximum of two
Gaussians
C–On the convexity of the generalized posynomial formulation for
transistor sizing
References
Index
Proof of convexity
Relation of a generalized posynomial program to a posynomial program

IAR

先收藏着，用的时候再来下

zh123456789

谢谢啊。

xcykii

thanks a lot

xcykii

2004年的，老书了

kebon22

classic
thank  u

wusuowei232

asdfsadfsa

lzj126

学以致用，下了一定要看，要不就不要下，哪有那么多时间浪费

MElik003

ddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddd

mtwumtwu

good reference for timing analysis