大家帮忙看下这个异步SRAM的控制代码有什么问题吗？

stephua

// sram_new.v
module sram_new(clk,reset,dowrite,doread,writedata,writeaddr,canread,canwrite,readaddr,
                      LB,CE,OE,WE,SRAM_DATA,SRAM_ADDR,readdata);
input clk;
input reset;
input dowrite;
input doread;
input [15:0] writedata;

input [17:0] writeaddr;
input [17:0] readaddr;
output canread;
output canwrite;
output LB;
output CE;
output OE;
output WE;
output [17:0] SRAM_ADDR;
output [15:0] readdata;
inout [15:0] SRAM_DATA;
reg [15:0] data_reg;
reg [15:0] data_temp;
reg [17:0] addr_reg;
reg [17:0] SRAM_ADDR;

reg canread;
reg canwrite;
reg CE;
reg WE;
reg OE;
reg LB;
reg [15:0] readdata;
reg [3:0] presState;
reg [3:0] nextState;
reg cnt;

parameter  stIdle   = 3'b000;
parameter  stWrite1 = 3'b001;
parameter  stWrite2 = 3'b010;
parameter  stWrite3 = 3'b011;
parameter  stRead1  = 3'b100;
parameter  stRead2  = 3'b101;
parameter  stRead3  = 3'b110;

assign SRAM_DATA = WE ? 16'hzzzz : data_reg;


always @(posedge clk)
begin
  if(!reset)
  begin
    presState <= stIdle;
  end
  else
  begin
    presState <= nextState;
  end
end
always @(*)
begin
  case(presState)
  stIdle:
  begin
    if(dowrite == 1'b1)
    begin
      nextState <= stWrite1;
      {canread,canwrite,CE,OE,WE,LB} <= 6'b001111;
    end
    else if(doread == 1'b1)
    begin
      nextState <= stRead1;
      {canread,canwrite,CE,OE,WE,LB} <= 6'b001001;
    end
    else
    begin
      nextState <= stIdle;
      {canread,canwrite,CE,OE,WE,LB} <= 6'b111111;
    end
  end
  stWrite1:
  begin
    nextState <= stWrite2;
    {canread,canwrite,CE,OE,WE,LB} <= 6'b000100;
    SRAM_ADDR <= writeaddr;
  end
  stWrite2:
  begin
    nextState <= stWrite3;
    {canread,canwrite,CE,OE,WE,LB} <= 6'b000100;
    data_reg <= writedata;
  end
  stWrite3:
  begin
    nextState <= stIdle;
    {canread,canwrite,CE,OE,WE,LB} <= 6'b001011;
  end
  stRead1:
  begin
    nextState <= stRead2;
    {canread,canwrite,CE,OE,WE,LB} <= 6'b000010;
    SRAM_ADDR <= readaddr;
  end
  stRead2:
  begin
    nextState <= stRead3;
    {canread,canwrite,CE,OE,WE,LB} <= 6'b000010;
    readdata <= SRAM_DATA;
  end
  
  stRead3:
  begin
    nextState <= stIdle;
    {canread,canwrite,CE,OE,WE,LB} <= 6'b001001;
  end
  default:
  begin
    nextState <= stIdle;
    {canread,canwrite,CE,OE,WE,LB} <= 6'b111111;
  end
  endcase
end

endmodule

用Synplify Pro综合之后，有个问题，提示说生成了3个锁存器，分别是SRAM_ADDR,data_reg,readdata.这3个锁存器对数据的读写有影响吗？是不是会造成数据干扰，比如说：如果将数据读出打到LED灯上，是不是LED等现保持一下先前的值，然后再更新为最新的值？该如何改才能去掉这个锁存器呢？
芯片型号：ISSI的异步SRAM IS61LV25616AL 板子上将UB、LB接到一块了，一次就操作16位数据，所以这里就只控制LB。
还有如果要高效读写该SRAM，该怎么改写程序呢？
希望大家多多提出意见与修改建议，非常感谢！

heartofknight

路过！！！！！