library ieee;
use ieee.std_logic_1164.all;
entity keyon is
port(en:in std_logic;
qut std_logic);
end entity keyon;
architecture one of keyon is
begin
process(en)
begin
if (en'event) and (en='1') then
q<='1';
end if;
end process;
end architecture one;
我的波形是全为高电平,这是为什么呢?
module SR_Latch(in,rst,q);
input in; // pulse signal input
input rst; // output reset signal(high active)
output q; // edge detection output. high active
always@(in or rst)
begin
if( rst == 1'b1)
q = #1 1'b0;
else
begin
if ( in == 1'b1)
q = #1 1'b1;
end
end
endmodule