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发表于 2010-4-27 10:36:42
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显示全部楼层
稍微改一下就好了呀，module switch_divclk(
clk_in,
clk_out,
switch_8bit_in
//test
//,clk_q1,clk_q2,count,count_clk,输入为0，则时钟输出为0，其它输入00000001为1分频，00000010为2分频……11111111
);
input clk_in;
input[7:0] switch_8bit_in;
output clk_out;
//,clk_q1,clk_q2;
reg[7:0] count_clk;
reg clk_q1,clk_q2;
//output[7:0] count,count_clk;
wire[7:0] count;
wire estop,switch_0,switch_1;
assign switch_0=(switch_8bit_in==8'b00000000)? 1'b1 : 1'b0;//assign switch_1=(switch_8bit_in==8'b00000001)? 1'b1 : 1'b0;assign estop=switch_0 || switch_1;assign count=switch_8bit_in[0] ? ((switch_8bit_in-1)/2+1) switch_8bit_in/2+1);//选择assign clk_out=switch_1 ? clk_in switch_8bit_in[0] ? (clk_q1 || clk_q2): clk_q1);always @(posedge estop or posedge clk_in)
if(estop)
begin
count_clk<=0;
clk_q1<=0;
end
else
if(count_clk<count-1)
begin
count_clk<=count_clk+1;
clk_q1<=1;
end
else
if(count_clk<switch_8bit_in-1)
begin
count_clk<=count_clk+1;
clk_q1<=0;
end
else
begin
count_clk<=0;
clk_q1<=0;
end
always @(posedge estop or negedge clk_in)
if(estop)
clk_q2<=0;
else
clk_q2<=clk_q1;
endmodule
仿真：
always #10 clk_in=!clk_in;
initial begin
// Initialize Inputs
clk_in = 0;
switch_8bit_in = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
switch_8bit_in = 8'b0010010;
end
没有问题，很好用，不过对几个assign语句不是很明白是什么意思 |
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