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发表于 2010-4-19 17:10:20
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别人的帖子复制一个如下:
at rtl coding and synthesis stage, normally the focus is on the timing/area/power optimization , designer do not want to be involed too much in the DFT task ,such as scan chain insertion and BIST test, therefore most people would like to insert the bist logic in the netlist instead of RTL.
actually the recommended way is to compile the bist block into gate level block first and then insert them into the design .
不知这个recommended way有哪些好处 |
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