这是什么工艺库

sally8512152

在做完dc等到sdf文件后对网表进行仿真的时候，需要一个verilog库，没这个库vcs总会说instance is unresolved 。库是.v文件，内容类似：
module AN03D1 (Y, A, B, C);
input  A, B, C;
output Y;
  and (Y, A, B, C);
specify
(        A   +=> Y) = (313.52:391.9 :470.28, 266.16:332.7:399.24);
(        B   +=> Y) = (313.92:392.4 :470.88, 253.12:316.4:379.68);
(        C   +=> Y) = (309.92:387.4 :464.88, 238.16:297.7:357.24);
endspecify
endmodule
这个库叫什么呀，怎么得到的呀（是公司给，还是要自己做）。谁有这种库，和这方面的资料。
哪位高手，能告诉我谢谢~~
我给分也行。email：sally851215@163.com

emerlai

for example, like this for .13. But you need the corresponding synopsys files.

emerlai

This is a gate-level verilog files for post-syn simulation. It often includes timing delay for each gates of different Fab process. I get it from my school.

zrzf23

look,look!!