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Our semiconductor industry is increasingly characterized by accelerated product obsolescence. As a result, business success is increasingly dependent upon the ability of development teams to deliver a shortest "time-to-market" product that meets customer requirements. Early product introduction means higher profit margins, lasting only until slower-to-market competitors enter and erode prices.
This intense cycle of market price erosion has been particularly evident in the personal computer industry over the last few years. Consumers are continually demanding quality products at lower cost but with increasing features. Semiconductor suppliers are, in turn, driven to develop system-on-a-chip (SoC) products utilizing VDSM (Very-Deep-Sub-Micron) technologies, just to remain competitive.
Several high performance tools and techniques have been developed over the past few years to mitigate somewhat this "time-to-market" pressure and to enable rapid design updates to meet evolving customer specifications. These changes have resulted in a redefinition of standard ASIC design flow methodologies. High level design languages, like VHDL and Verilog, have displaced schematic capture, thus promoting design reuse. Dynamic simulation has given way to formal verification and static timing analysis. In addition, synthesis engines have become more sophisticated, targeting complex designs containing millions of gates and large IP cores. It is now estimated that the number of gates in a complex ASIC will approach 10 million early in the next decade.
Successfully achieving these levels of integration in a time-to-market focused development environment will require an intimate knowledge of ASIC design flow in the VDSM realm and a complex integration of products offered by multiple EDA tool vendors.
This book, written by Himanshu Bhatnagar, provides a comprehensive overview of the ASIC design flow targeted for VDSM technologies using the Synopsys suite of tools. It emphasizes the practical issues faced by the semiconductor design engineer in terms of synthesis and the integration of front-end and back-end tools. Traditional design methodologies are challenged and unique solutions are offered to help define the next-generation of ASIC design flows. The author provides numerous practical examples derived from real-world situations that will prove valuable to practicing ASIC design engineers as well as to students of advanced VLSI courses in ASIC design.
Dr. Dwight W. Decker Chairman and CEO, Conexant Systems, Inc. (Formerly, Rockwell Semiconductor Systems) Newport Beach, California, U.S.A.
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发表于 2004-9-20 19:22:04
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