请教各位达人，关于Calibre LVS时Port number的问题

ljj_16 · 发表于 2009-10-6 16:12:36

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小弟最近用Calibre做LVS，遇到source和layout的port number不match的情况，下面是lvs report。布线用的是SOC encounter 7.1

               ##################################################
               ##                                           ##
               ##       C A L I B R E S Y S T E M       ##
               ##                                           ##
               ##          L V S R E P O R T             ##
               ##                                           ##
               ##################################################

                           OVERALL COMPARISON RESULTS

               # #       #####################
               # #       #                #
                  #          #    INCORRECT    #
               # #       #                #
               # #       #####################

  Error: Different numbers of ports.

**************************************************************************************************************
                                    CELL  SUMMARY
**************************************************************************************************************
  Result       Layout                      Source
  ----------- -----------                --------------
  INCORRECT    shiftin                      shiftin

**************************************************************************************************************
                                    LVS PARAMETERS
**************************************************************************************************************

o LVS Setup:
LVS COMPONENT TYPE PROPERTY          element
LVS COMPONENT SUBTYPE PROPERTY       model
LVS PIN NAME PROPERTY                phy_pin
LVS POWER NAME                      "VDD"
LVS GROUND NAME                      "VSS"
LVS CELL SUPPLY                      NO
LVS RECOGNIZE GATES                   ALL
LVS IGNORE PORTS                      NO
LVS CHECK PORT NAMES                YES
LVS IGNORE TRIVIAL NAMED PORTS       NO
LVS BUILTIN DEVICE PIN SWAP          NO
LVS ALL CAPACITOR PINS SWAPPABLE    NO
LVS DISCARD PINS BY DEVICE          NO
LVS SOFT SUBSTRATE PINS             NO
LVS INJECT LOGIC                      NO
LVS EXPAND UNBALANCED CELLS          YES
LVS EXPAND SEED PROMOTIONS          NO
LVS PRESERVE PARAMETERIZED CELLS    NO
LVS GLOBALS ARE PORTS                YES
LVS REVERSE WL                      NO
LVS SPICE PREFER PINS                NO
LVS SPICE SLASH IS SPACE             YES
LVS SPICE ALLOW FLOATING PINS       YES
LVS SPICE ALLOW INLINE PARAMETERS    UNSPECIFIED
LVS SPICE ALLOW UNQUOTED STRINGS    NO
LVS SPICE CONDITIONAL LDD             NO
LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
LVS SPICE IMPLIED MOS AREA          NO
// LVS SPICE MULTIPLIER NAME
LVS SPICE OVERRIDE GLOBALS          NO
LVS SPICE REDEFINE PARAM             NO
LVS SPICE REPLICATE DEVICES          NO
LVS SPICE STRICT WL                   NO
// LVS SPICE OPTION
LVS STRICT SUBTYPES                   NO
LAYOUT CASE                         NO
SOURCE CASE                         NO
LVS COMPARE CASE                      NO
LVS DOWNCASE DEVICE                   NO
LVS REPORT MAXIMUM                   50
LVS PROPERTY RESOLUTION MAXIMUM       ALL
// LVS SIGNATURE MAXIMUM
LVS FILTER UNUSED OPTION             AC AD AF AG C F G RC RE RG YB ZC ZD
// LVS REPORT OPTION
LVS REPORT UNITS                      YES
// LVS NON USER NAME PORT
// LVS NON USER NAME NET
// LVS NON USER NAME INSTANCE

               CELL COMPARISON RESULTS ( TOP LEVEL )

               # #       #####################
               # #       #                #
                  #          #    INCORRECT    #
               # #       #                #
               # #       #####################

  Error: Different numbers of ports (see below).
LAYOUT CELL NAME:       shiftin
SOURCE CELL NAME:       shiftin
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
            Layout Source       Component Type
            ------ ------       --------------
Ports:          38       38
Nets:          550    551 *
Instances:       481    481       MN (4 pins)
               481    481       MP (4 pins)
            ------ ------
Total Inst:    962    962

NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
            Layout Source       Component Type
            ------ ------       --------------
Ports:          38       37 *
Nets:          262    262
Instances:       193    193       INV (2 pins)
                  96       96       SDW2 (3 pins)
                  32       32       SDW3 (4 pins)
                  96       96       SUP2 (3 pins)
                  32       32       SPUP_2_1 (4 pins)
            ------ ------
Total Inst:    449    449

   * = Number of objects in layout different from number in source.

**************************************************************************************************************
                              INCORRECT OBJECTS
**************************************************************************************************************

LEGEND:
-------
  ne  = Naming Error (same layout name found in source
      circuit, but object was matched otherwise).

**************************************************************************************************************
                                 INCORRECT PORTS
DISC#  LAYOUT NAME                                              SOURCE NAME
**************************************************************************************************************
  1 N2 on net: N2                                           ** missing port **

**************************************************************************************************************
                           INFORMATION AND WARNINGS
**************************************************************************************************************

               Matched Matched Unmatched Unmatched Component
               Layout    Source    Layout    Source Type
               ------- ------- --------- --------- ---------
Ports:             37       37          1          0
Nets:             262       262          0          0
Instances:       193       193          0          0 INV
                     96       96          0          0 SDW2
                     32       32          0          0 SDW3
                     96       96          0          0 SUP2
                     32       32          0          0 SPUP_2_1
               ------- ------- --------- ---------
Total Inst:       449       449          0          0

o Statistics:
1 passthrough source net was deleted.

o Layout Names That Are Missing In The Source:
Ports:       N2

o Initial Correspondence Points:
Ports:       VDD VSS RESET_SHIFT CLOCK Q[1] Q[29] Q[27] Q[0] Q[26] Q[30] Q[6] Q[2] Q[23]
               Q[8] Q[13] Q[16] Q[21] Q[5] IN Q[31] Q[25] Q[4] Q[7] Q[24] Q[28] Q[3] Q[10]
               Q[14] Q[17] Q[22] Q[20] Q[9] Q[19] Q[12] Q[15] Q[18] Q[11]
Nets:       N2

里面不match的port N2在schematic上是内部连线，而layout上把它认成了port。
这个block是一个大block里面的一个小block，大的block在做LVS时也遇到了内部连线被认成外部port的问题，造成大的block的layout有几千个port，而schematic只有几十个。有大大说是block被flatten了，小弟把从encounter得到的GDS文件导入到Cadence Virtuoso时生成的Hierarchy Listing显示中间的层次都没有体现出来。所以小弟觉得可能是在encounter里面做layout时候block被flatten了，但是小弟基本上都是按tutorial来做的，不知道哪个地方设错了，导致flatten？
小弟刚接触数字后端不久，分析难免出错，不知道是不是其他原因导致，希望各位大大指点，小弟感激不尽！

jediai · 发表于 2009-10-7 00:38:54

Calibre是这样的，一个很小的错都能分析出大批的错误（包括电源地的问题），虽然有问题一定会报出来，但是单查还是有些困难的（报错的地方经常是被影响的，本身没问题），可以和Hercules等软件一起做，同时根据报错的类型等查看电路，保证了Instance数量相等后问题就不大了，一般都是粗心、端口导致的LVS错误