asking for helping

hypee

this is vhdl model  :     if clk'event and clk='1' then
if I convert this model to verilog :
   if (clk == 1'b1)  ....

atuhappy

[这个贴子最后由atuhappy在 2004/06/15 08:43pm 第 1 次编辑]

always@(posedge clk)
beign
end

hypee

thank you!

xudongyang

By the way ,I'm afraid  you should  substitute your title for asking for help!