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发表于 2004-6-18 15:44:52
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[讨论]两个进程共用一组输出的寄存器?
module counter (reset_n, data_load, clk, c1, data_out);
input reset_n;
input data_load;
input clk;
input [7:0] c1;
output [7:0] data_out;
reg [7:0] data_out;
always @(posedge clk) begin
if (~reset_n) data_out <= 8'd0;
else if (data_load) data_out <= c1;
else data_out <= data_out + 8'd1;
end
endmodule
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