JSSC （IEEE Journal of solid state circuits）2009年第二期

stepwm

模拟芯片设计领域的最权威的杂志JSSC （IEEE Journal of solid state circuits）2009年二月份全集
  文件有点大 ，另外网站对上传文件大小又限制，所以只有分成这么多份发上来了 ，请大家原谅~
A 1-V +31 dBm IIP3, Reconfigurable, Continuously Tunable, Power-Adjustable Active-RC LPF
A 3.1 GHz–8.0 GHz Single-Chip Transceiver for MB-OFDM UWB in 0.18-$mu$ m CMOS Process
A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS
A 750 Mb per s, 12 pJ per b, 6-to-10 GHz CMOS IR-UWB Transmitter With Embedded On-Chip Antenna
A Fully Integrated 7.3 kV HBM ESD-Protected Transformer-Based 4.5–6 GHz CMOS LNA
A Low-Power, Linearized, Ultra-Wideband LNA Design Technique
A Rail-To-Rail Class-AB Amplifier With an Offset Cancellation for LCD Drivers
A RF to DC Voltage Conversion Model for Multi-Stage Rectifiers in UHF RFID Transponders
A Single-Chip Ultra-Wideband Receiver With Silicon Integrated Antennas for Inter-Chip Wireless Interconnection
A Single-Inductor Step-Up DC-DC Switching Converter With Bipolar Outputs for Active Matrix OLED Mobile Display Panels
A Slew Controlled LVDS Output Driver Circuit in 0.18 $mu$m CMOS Technology
A Wideband Power Detection System Optimized for the UWB Spectrum
An Energy Efficient 40 Kb SRAM Module With Extended Read-Write Noise Margin in 0.13 $mu$m CMOS
An Improved Active Decoupling Capacitor for “Hot-Spot” Supply Noise Reduction in ASIC Designs
Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems
Analysis of the Influence of Substrate on the Performance of On-Chip MOS Decoupling Capacitors
Combined Linear and $Delta$-Modulated Switch-Mode PA Supply Modulator for Polar Transmitters
Design and Analysis of Actively-Deskewed Resonant Clock Networks
Design and Measurement of a CT $DeltaSigma$ ADC With Switched-Capacitor Switched-Resistor Feedback
Energy–Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example
Fast Low Power eDRAM Hierarchical Differential Sense Amplifier
HDTV1080p H.264-AVC Encoder Chip Design and Performance Analysis
High-Speed Single-Ended Parallel Link Based on Three-Level Differential Encoding
LC PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS
Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator
Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers
Robust SRAM Design via BIST-Assisted Timing-Tracking (BATT)
SRAM Cell Stability-A Dynamic Perspective
Systematic Transistor and Inductor Modeling for Millimeter-Wave Design

razoruser

thanks

[ 本帖最后由 razoruser 于 2009-6-13 19:20 编辑 ]

razoruser

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razoruser

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razoruser

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caosl

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razoruser

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razoruser

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razoruser

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razoruser

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