求几篇 JSSC CDR文章

mcgrady · 发表于 2015-10-26 10:22:01

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谢谢！

1. J. Lee et al., “Analysis and Modeling of Bang-Bang Clock and Data Recovery
Circuits”, IEEE Journal of Solid-State Circuits, Vol. 39, No. 9, September 2004, pp.
1571-1580.
2. J. Sonntag et al., “A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s
Binary Links”, IEEE Journal of Solid-State Circuits, Vol. 41, No. 8, August 2006, pp.
1867-1875.
3. P. K. Hanumolu, et al., “A Wide-Tracking Range Clock and Data Recovery Circuit”,
IEEE Journal of Solid-State Circuits, Vol. 43, No. 2, February 2008, pp. 425-439.

lwjee · 发表于 2015-10-26 12:14:11

回复 1# mcgrady

A Wide-Tracking Range Clock and Data Recovery Circuit.pdf (1.95 MB, 下载次数: 68 )

Analysis and Modeling of Bang-Bang Clock and Data Recovery Circuits.PDF (1.32 MB, 下载次数: 64 )

A Digital Clock and Data Recovery Architecture.pdf (1.06 MB, 下载次数: 64 )
刚好都有。

mcgrady · 发表于 2015-10-26 14:38:17

回复 2# lwjee

谢谢！

mcgrady · 发表于 2015-10-26 16:14:06

回复 2# lwjee

再求几篇，您这还有吗

  A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects  -- Chen, S.

A 1.6Gbps Digital Clock and Data Recovery Circuit ---  Hanumolu, P.K.      ;

Digital clock and data recovery circuit design: Challenges and tradeoffs  -- Talegaonkar, M.      ;