Writing Testbenches - Functional Verification of HDL Models(Janick Bergeron)

wadezhu · 发表于 2009-5-1 09:44:02

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Take a survey  of the  books  about Verilog  or VHDL currently  avail-
able.  You  will  notice  that  the majority  of  the  pages  are  devoted  to
explaining  the details  of the  languages.  In addition,  several chapters
are  focused  on  the  synthesizeable  coding  style  -  or  RTL  -  replete
with examples.  Some books  are even devoted entirely  to the  subject
of RTL  coding.
When  verification  is  addressed,  only  one  or  two  chapters  are  dedi-
cated  to  the topic. And often, the primary  focus  is to introduce more
language  constructs.  Verification  is  often  presented  in  a  very  rudi-
mentary  fashion,  using  simple  techniques  that  become  tedious  in
large-scale, real-life designs.

jcchan · 发表于 2009-5-1 10:04:13

Thanks!!!!

lengguang1587 · 发表于 2009-12-23 21:20:58

谢谢分享！～

lengguang1587 · 发表于 2009-12-23 21:22:40

请问是否为打印版的？

cardchen · 发表于 2010-1-14 23:36:03

very very good!!

飞的更高8 · 发表于 2010-1-28 14:05:03

1# wadezhu

飞的更高8 · 发表于 2010-1-28 14:10:19

1# wadezhu

zhang_career · 发表于 2010-4-14 13:56:53

haohaohao

zhang_career · 发表于 2010-4-14 13:58:25

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zhang_career · 发表于 2010-4-14 13:59:50

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Writing Testbenches - Functional Verification of HDL Models(Janick Bergeron)

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