Cadence招聘前端设计工程师-FPGA/MMP

kengteng

Cadence招聘前端设计工程师-FPGA/MMP

Title: Lead Design Engineer-FPGA
Location： SH
更多职位信息敬请关注Cadence公众微信平台：Cadence微招聘
If you have interest, PLS send your update CV to job_china@cadence.com


Title: Lead FPGA Design Engineer
                               
Position Description:       
-Responsible for designing and developing sub-systems and modules or components of hardware based verification products.
-In addition modifying, updating and productizing existing hardware based verification products. Perform as individual contributor on FPGA based design projects involving board design, RTL design, verification, productizing and documentation.
-Work on diverse problems related to FPGA design, simulation or verification issues.

                               
Position Requirements:       
-The position requires BSEE, or equivalent, with a minimum of 4 yrs of industry experience in designing hardware systems.
-Must have excellent communication skills, both written and verbal. Technical expertise in FPGA design for either Altera or Xilinx products is required. Experience in FPGA design methodologies including high speed design, serial protocols and FPGA timing closure is desired.
-In addition RTL design knowledge using verilog is required along with experience in using RTL verification tools and flows. Verification using with Cadence simulation products is desired. -Experience with scripting languages like Perl, TCL C-shell is strongly recommended. Experience with PCB tools is also desired.


Lead Design Engineer--Memory Modeling Portfolio
Location： SH

Position Description:       
1.Responsible for scheduling, designing, developing, and supporting IP models of system level memory such as SDRAM (LPDDR, HBM), NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS models for use on hardware based verification products. Also responsible for updating, maintaining, documenting, and supporting existing system level memory model products. 2.Perform as individual contributor for RTL design, verification, productizing, and documentation of memory IP. Interface with internal and external customers to work on diverse problems and solutions related to emulation, simulation, or verification. Perform as team member toward cross verification of and cross training in memory IP as well as in developing and using lifecycle processes to ensure product quality.

Position Requirements:       
Essential:
1.The position requires BSEE, or equivalent, with a minimum of 4 yrs of industry experience in designing hardware systems.
2.Must have excellent communication skills with both written and spoken English. RTL design knowledge using Verilog/SystemVerilog is required along with experience using RTL verification tools and flows.
3.Debugging experience. Experience with team-wide collaboration tools and process. Drive and ability to schedule workload and plan own tasks effectively.
4.Strongly recommended: Verification experience using Cadence simulation and/or emulation products is highly desired. Programming experience with scripting languages like Perl, TCL, C-shell is strongly recommended.
5.Experience in memory sub-system design and operation is strongly recommended.

amarnath1683

which domain has good futur

prakash2016

thanks