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练习DFT中的SCAN插入。
源代码如下：
module dfttest(clk,reset, // SCAN PIN SCAN
SCAN_TEST,
SCAN_CLK,
SCAN_ENA,
PIN_SI,
PIN_SO,
pulse
);
input clk,reset;
output pulse;
input SCAN_TEST,SCAN_CLK,SCAN_ENA,PIN_SI;
output PIN_SO;
reg [1:0] counter;
wire clkin;
assign clkin = SCAN_TEST ? (SCAN_CLK) : clk;
always @(posedge clkin or negedge reset)
begin
if (~reset)
counter <=0;
else
counter<=counter +1;
end
assign pulse = &counter;
endmodule
脚本文件如下：
reset_design
remove_design -all
read_file -format verilog /home/TEMP/source20090428/dfttest.v
current_design dfttest
link
uniquify
#set_units -time ns -resistance kOhm -capacitance pF -voltage V -current uA
set_operating_conditions -min_library sagehs_smic_013g_ff_1p32v_0c -min sagehs_smic_013g_ff_1p32v_0c -max_library sagehs_smic_013g_ff_1p32v_0c -max sagehs_smic_013g_ff_1p32v_0c
set auto_wire_load_selection true
#set_max_area 1500000
set_max_fanout 16 [get_designs *]
set_max_capacitance 2 [get_designs *]
set_load 0.1 [get_nets * ]
set_load 50 [all_outputs]
set bind_unused_hierarchical_pins true
current_design dfttest
create_clock -name "SCLK" -period 20 -waveform { 0.000 10.000 } { clk }
set_dont_touch_network SCLK
#******************************* insert scan **************************************
set_scan_configuration -style multiplexed_flip_flop
set_scan_configuration -clock_mixing no_mix
set_scan_configuration -internal_clocks single
set_dft_signal -view existing_dft -type TestMode -port SCAN_TEST -active_state 1
set_dft_signal -view existing_dft -type Reset -port reset -active_state 0
set_dft_signal -view existing_dft -type ScanClock -port SCAN_CLK -timing {45 55}
set_dft_signal -view existing_dft -type ScanEnable -port SCAN_ENA -active_state 1
set_dft_signal -view spec -type ScanDataIn -port PIN_SI -active_state 1
set_dft_signal -view spec -type ScanDataOut -port PIN_SO -active_state 1
set_scan_configuration -chain_count 1
set_scan_path -view spec c0 -scan_data_in PIN_SI -scan_data_out PIN_SO
set_autofix_configuration -type clock -control_signal SCAN_TEST -test_data PIN_SI
set_autofix_configuration -type reset -control_signal SCAN_TEST -test_data PIN_SO
compile -scan
create_test_protocol
preview_dft
insert_dft
report_constraint -all_violators
report_scan_path
estimate_test_coverage
write_test_protocol -output /home/TEMP/source20090428/dfttest.spf
#*********************** * end insert scan *****************************
执行结果如下：
Starting shell in XG mode...
dc_shell-t> gui_start
design_vision-xg-t> uplevel #0 source /home/TEMP/source20090428/dfttest.tcl
Error: Current design is not defined. (UID-4)
Loading db file '/home/SMIC13/synopsys/sagehs_smic_013g_ff_1p32v_0c.db'
Loading db file '/home/SMIC13/synopsys/sagehs_smic_013g_ff_1p32v_m40c.db'
Loading db file '/home/SMIC13/synopsys/sagehs_smic_013g_ss_1p08v_125c.db'
Loading db file '/home/SMIC13/synopsys/sagehs_smic_013g_tt_1p2v_25c.db'
Loading db file '/home/synopsys/dc2007/libraries/syn/gtech.db'
Loading db file '/home/synopsys/dc2007/libraries/syn/standard.sldb'
Loading link library 'sagehs_smic_013g_ff_1p32v_0c'
Loading link library 'sagehs_smic_013g_ff_1p32v_m40c'
Loading link library 'sagehs_smic_013g_ss_1p08v_125c'
Loading link library 'sagehs_smic_013g_tt_1p2v_25c'
Loading link library 'gtech'
Loading verilog file '/home/TEMP/source20090428/dfttest.v'
Detecting input file type automatically (-rtl or -netlist).
Running DC verilog reader
Reading with Presto HDL Compiler (equivalent to -rtl option).
Running PRESTO HDLC
Compiling source file /home/TEMP/source20090428/dfttest.v
Inferred memory devices in process
in routine dfttest line 16 in file
'/home/TEMP/source20090428/dfttest.v'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| counter_reg | Flip-flop | 2 | Y | N | Y | N | N | N | N |
===============================================================================
Presto compilation completed successfully.
Current design is now '/home/TEMP/source20090428/dfttest.db:dfttest'
Loaded 1 design.
Current design is 'dfttest'.
Current design is 'dfttest'.
Linking design 'dfttest'
Using the following designs and libraries:
--------------------------------------------------------------------------
dfttest /home/TEMP/source20090428/dfttest.db
sagehs_smic_013g_ff_1p32v_0c (library) /home/SMIC13/synopsys/sagehs_smic_013g_ff_1p32v_0c.db
sagehs_smic_013g_ff_1p32v_m40c (library) /home/SMIC13/synopsys/sagehs_smic_013g_ff_1p32v_m40c.db
sagehs_smic_013g_ss_1p08v_125c (library) /home/SMIC13/synopsys/sagehs_smic_013g_ss_1p08v_125c.db
sagehs_smic_013g_tt_1p2v_25c (library) /home/SMIC13/synopsys/sagehs_smic_013g_tt_1p2v_25c.db
Using operating conditions 'sagehs_smic_013g_ff_1p32v_0c' found in library 'sagehs_smic_013g_ff_1p32v_0c'.
Using operating conditions 'sagehs_smic_013g_ff_1p32v_0c' found in library 'sagehs_smic_013g_ff_1p32v_0c'.
Current design is 'dfttest'.
Accepted scan configuration for modes: all_dft
Accepted scan configuration for modes: all_dft
Accepted scan configuration for modes: all_dft
Accepted dft signal specification for modes: all_dft
Accepted dft signal specification for modes: all_dft
Accepted dft signal specification for modes: all_dft
Accepted dft signal specification for modes: all_dft
Accepted dft signal specification for modes: all_dft
Accepted dft signal specification for modes: all_dft
Accepted scan configuration for modes: all_dft
Accepted scan path specification for mode: Internal_scan
Error: TestMode or ScanEnable signal type not specified for the port SCAN_TEST. (TESTXG-10)
Discarded Autofix configuration specifications.
Error: TestMode or ScanEnable signal type not specified for the port SCAN_TEST. (TESTXG-10)
Discarded Autofix configuration specifications.
Information: Choosing a test methodology will restrict the optimization of sequential cells. (UIO-12)
Information: Evaluating DesignWare library utilization. (UISN-27)
============================================================================
| DesignWare Building Block Library | Version | Available |
============================================================================
| Basic DW Building Blocks | Z-2007.03-DWBB_0710 | * |
| Licensed DW Building Blocks | | |
============================================================================
Information: There are 4 potential problems in your design. Please run 'check_design' for more information. (LINT-99)
Warning: Removing some annotated net capacitances from design 'dfttest'. (OPT-800)
Warning: Removing some annotated net resistances from design 'dfttest'. (OPT-801)
Warning: Operating condition sagehs_smic_013g_ff_1p32v_0c set on design dfttest has different process,
voltage and temperatures parameters than the parameters at which target library
sagehs_smic_013g_ff_1p32v_m40c is characterized. Delays may be inaccurate as a result. (OPT-998)
Beginning Pass 1 Mapping
------------------------
Processing 'dfttest'
Updating timing information
Information: Updating design information... (UID-85)
Beginning Mapping Optimizations (Medium effort)
-------------------------------
ELAPSED WORST NEG TOTAL NEG DESIGN
TIME AREA SLACK SLACK RULE COST ENDPOINT
--------- --------- --------- --------- --------- -------------------------
0:00:06 260.1 0.00 0.0 79.4
0:00:06 141.5 0.00 0.0 79.4
0:00:06 141.5 0.00 0.0 79.4
0:00:06 141.5 0.00 0.0 79.4
0:00:06 141.5 0.00 0.0 79.4
0:00:06 141.5 0.00 0.0 79.4
0:00:06 141.5 0.00 0.0 79.4
0:00:06 141.5 0.00 0.0 79.4
0:00:06 141.5 0.00 0.0 79.4
Beginning Delay Optimization Phase
----------------------------------
ELAPSED WORST NEG TOTAL NEG DESIGN
TIME AREA SLACK SLACK RULE COST ENDPOINT
--------- --------- --------- --------- --------- -------------------------
0:00:06 141.5 0.00 0.0 79.4
0:00:06 141.5 0.00 0.0 79.4
Beginning Design Rule Fixing (max_transition) (max_capacitance)
----------------------------
ELAPSED WORST NEG TOTAL NEG DESIGN
TIME AREA SLACK SLACK RULE COST ENDPOINT
--------- --------- --------- --------- --------- -------------------------
0:00:06 141.5 0.00 0.0 79.4
0:00:07 164.4 0.00 0.0 59.0
Beginning Area-Recovery Phase (cleanup)
-----------------------------
ELAPSED WORST NEG TOTAL NEG DESIGN
TIME AREA SLACK SLACK RULE COST ENDPOINT
--------- --------- --------- --------- --------- -------------------------
0:00:07 164.4 0.00 0.0 59.0
0:00:07 164.4 0.00 0.0 59.0
0:00:07 158.1 0.00 0.0 59.0
0:00:07 158.1 0.00 0.0 59.0
0:00:07 158.1 0.00 0.0 59.0
0:00:07 158.1 0.00 0.0 59.0
0:00:07 158.1 0.00 0.0 59.0
0:00:07 158.1 0.00 0.0 59.0
0:00:07 158.1 0.00 0.0 59.0
0:00:07 158.1 0.00 0.0 59.0
0:00:07 158.1 0.00 0.0 59.0
0:00:07 158.1 0.00 0.0 59.0
Loading db file '/home/SMIC13/synopsys/sagehs_smic_013g_ff_1p32v_0c.db'
Loading db file '/home/SMIC13/synopsys/sagehs_smic_013g_ff_1p32v_m40c.db'
Loading db file '/home/SMIC13/synopsys/sagehs_smic_013g_ss_1p08v_125c.db'
Loading db file '/home/SMIC13/synopsys/sagehs_smic_013g_tt_1p2v_25c.db'
Optimization Complete
---------------------
In mode: all_dft...
Information: Starting test protocol creation. (TEST-219)
...reading user specified clock signals...
Information: Identified system/test clock port SCAN_CLK (45.0,55.0). (TEST-265)
...reading user specified asynchronous signals...
Information: Identified active low asynchronous control port reset. (TEST-266)
Information: Starting test design rule checking. (TEST-222)
Test Design rule checking did not find violations
Information: Test design rule checking completed. (TEST-123)
Architecting Scan Chains
****************************************
Preview_dft report
For : 'Insert_dft' command
Design : dfttest
Version: Z-2007.03-SP5
Date : Tue Apr 28 20:55:12 2009
****************************************
Number of chains: 1
Scan methodology: full_scan
Scan style: multiplexed_flip_flop
Clock domain: no_mix
Scan enable: SCAN_ENA (no hookup pin)
Scan chain 'c0' (PIN_SI --> PIN_SO) contains 2 cells
************ Test Point Plan Report ************
Total number of test points : 0
Number of Autofix test points: 0
Number of Wrapper test points: 0
Number of test modes : 0
Number of test point enables : 0
Number of data sources : 0
Number of data sinks : 0
**************************************************
Information: Starting test design rule checking. (TEST-222)
Test Design rule checking did not find violations
Information: Test design rule checking completed. (TEST-123)
Architecting Scan Chains
Routing Scan Chains
Routing Global Signals
Mapping New Logic
Beginning Mapping Optimizations
-------------------------------
ELAPSED WORST NEG TOTAL NEG DESIGN
TIME AREA SLACK SLACK RULE COST ENDPOINT
--------- --------- --------- --------- --------- -------------------------
Beginning Phase 1 Design Rule Fixing (max_transition) (max_capacitance)
------------------------------------
ELAPSED WORST NEG TOTAL NEG DESIGN
TIME AREA SLACK SLACK RULE COST ENDPOINT
--------- --------- --------- --------- --------- -------------------------
0:00:16 241.4 0.00 0.0 233.5 counter[1]
0:00:16 241.4 0.00 0.0 233.5 counter[1]
0:00:16 241.4 0.00 0.0 233.5 counter[1]
0:00:16 247.6 0.00 0.0 233.4 net75
Beginning Phase 2 Design Rule Fixing (max_transition) (max_capacitance)
------------------------------------
ELAPSED WORST NEG TOTAL NEG DESIGN
TIME AREA SLACK SLACK RULE COST ENDPOINT
--------- --------- --------- --------- --------- -------------------------
Resetting current test mode
Beginning Mapping Optimizations
-------------------------------
Beginning Phase 1 Design Rule Fixing (max_transition) (max_capacitance)
------------------------------------
ELAPSED WORST NEG TOTAL NEG DESIGN
TIME AREA SLACK SLACK RULE COST ENDPOINT
--------- --------- --------- --------- --------- -------------------------
Beginning Phase 2 Design Rule Fixing (max_transition) (max_capacitance)
------------------------------------
ELAPSED WORST NEG TOTAL NEG DESIGN
TIME AREA SLACK SLACK RULE COST ENDPOINT
--------- --------- --------- --------- --------- -------------------------
****************************************
Report : constraint
-all_violators
Design : dfttest
Version: Z-2007.03-SP5
Date : Tue Apr 28 20:55:13 2009
****************************************
max_transition
Required Actual
Net Transition Transition Slack
-----------------------------------------------------------------
PIN_SO 0.74 125.36 -124.62 (VIOLATED)
pulse 0.74 11.42 -10.67 (VIOLATED)
max_capacitance
Required Actual
Net Capacitance Capacitance Slack
-----------------------------------------------------------------
PIN_SO 0.17 50.00 -49.83 (VIOLATED)
pulse 1.71 50.00 -48.29 (VIOLATED)
****************************************
Report : Scan path
Design : dfttest
Version: Z-2007.03-SP5
Date : Tue Apr 28 20:55:13 2009
****************************************
========================================
TEST MODE: Internal_scan
VIEW : Specification
========================================
Scan_path ScanDataIn (h) ScanDataOut (h) ScanEnable (h)
--------------- --------------- --------------- ---------------
c0 PIN_SI (-) PIN_SO (-) -
========================================
TEST MODE: Internal_scan
VIEW : Specification
========================================
Scan_path Cell_# Instance_name
--------- ------ -------------
c0 No scan cells to report
****************************************
Report : Scan path
Design : dfttest
Version: Z-2007.03-SP5
Date : Tue Apr 28 20:55:13 2009
****************************************
========================================
TEST MODE: Internal_scan
VIEW : Existing DFT
========================================
========================================
AS SPECIFIED BY USER
========================================
========================================
AS BUILT BY insert_dft
========================================
Scan_path Len ScanDataIn ScanDataOut ScanEnable MasterClock SlaveClock
----------- ----- ----------- ----------- ----------- ----------- -----------
I c0 2 PIN_SI PIN_SO SCAN_ENA SCAN_CLK -
========================================
TEST MODE: Internal_scan
VIEW : Existing DFT
========================================
========================================
AS SPECIFIED BY USER
========================================
========================================
AS BUILT BY insert_dft
========================================
Scan_path Cell_# Instance_name Clocks
--------- ------ ------------- ------
I c0 0 counter_reg[0] SCAN_CLK
1 counter_reg[1]
Using test protocol in memory.
Starting test coverage estimation ...
94 faults were added to fault list.
ATPG performed for stuck fault model using internal pattern source.
----------------------------------------------------------
#patterns #faults #ATPG faults test process
stored detect/active red/au/abort coverage CPU time
--------- ------------- ------------ -------- --------
Begin deterministic ATPG: #uncollapsed_faults=42, abort_limit=10...
0 42 0 0/0/0 92.55% -0.00
Pattern Summary Report
-----------------------------------------------
#internal patterns 0
-----------------------------------------------
Uncollapsed Stuck Fault Summary Report
-----------------------------------------------
fault class code #faults
------------------------------ ---- ---------
Detected DT 87
Possibly detected PT 0
Undetectable UD 0
ATPG untestable AU 7
Not detected ND 0
-----------------------------------------------
total faults 94
test coverage 92.55%
-----------------------------------------------
Information: The test coverage above may be inferior
than the real test coverage with customized
protocol and test simulation library.
Writing test protocol file '/home/TEMP/source20090428/dfttest.spf' for mode 'Internal_scan'...
design_vision-xg-t>
Current design is 'dfttest'.
在插入DFT的时候用到了下面两条命令，可是都不能执行，清大家帮忙看看！就是下面两条（蓝色是命令，红色是反馈）
set_autofix_configuration -type clock -control_signal SCAN_TEST -test_data PIN_SI
Error: TestMode or ScanEnable signal type not specified for the port SCAN_TEST. (TESTXG-10)
Discarded Autofix configuration specifications.
0
set_autofix_configuration -type reset -control_signal SCAN_TEST -test_data PIN_SO
Error: TestMode or ScanEnable signal type not specified for the port SCAN_TEST. (TESTXG-10)
Discarded Autofix configuration specifications.
0
下面是全部的DFT插入命令，反馈都正常，就是最后两条不对 。
这些命令都在compile之前。
set_scan_configuration -style multiplexed_flip_flop
set_scan_configuration -clock_mixing mix_clocks
set_scan_configuration -internal_clocks single
set_dft_signal -view existing_dft -type TestMode -port SCAN_TEST -active_state 1
set_dft_signal -view existing_dft -type Reset -port RESET_N -active_state 0
set_dft_signal -view existing_dft -type ScanClock -port SCAN_CLK -timing {45 55}
set_dft_signal -view existing_dft -type ScanEnable -port SCAN_ENA -active_state 1
set_dft_signal -view spec -type ScanDataIn -port PIN_SI -active_state 1
set_dft_signal -view spec -type ScanDataOut -port PIN_SO -active_state 1
set_scan_configuration -chain_count 1
set_scan_path -view spec c0 -scan_data_in PIN_SI -scan_data_out PIN_SO
set_dft_configuration -fix_clock enable
set_dft_configuration -fix_reset enable
set_autofix_configuration -type clock -control_signal SCAN_TEST -test_data PIN_SI
Error: TestMode or ScanEnable signal type not specified for the port SCAN_TEST. (TESTXG-10)
Discarded Autofix configuration specifications.
0
set_autofix_configuration -type reset -control_signal SCAN_TEST -test_data PIN_SO
Error: TestMode or ScanEnable signal type not specified for the port SCAN_TEST. (TESTXG-10)
Discarded Autofix configuration specifications.
0
[ 本帖最后由 helte320 于 2009-4-28 20:55 编辑 ] |
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