DFT 中set_autofix_configuration命令不对，希望高手指点原因（复代码）

xiaocanmeng · 发表于 2011-6-30 21:20:15

#################################################################
# Synopsys DC script
#################################################################
set design_top       [getenv DESIGN_TOP]
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
# DC setup
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
source library_setup.tcl
source common_setup.tcl

#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
# Analyze & elaborate RTL source
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
read_file -format verilog ./dfttest.v
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
# Link design
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
link

#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
# Check design
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
check_design

#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
# Apply constraints
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
set auto_wire_load_selection true
#set_max_area 1500000
set_max_fanout 16 [get_designs *]
set_max_capacitance 2 [get_designs *]
set_load 0.1  [get_nets * ]
set_load 50 [all_outputs]
set bind_unused_hierarchical_pins true
current_design dfttest
  create_clock -name "Fun_CLK" -period 20 -waveform { 0.000 10.000  }  { clk  }
set_dont_touch_network clk

#******************************* insert scan **************************************
compile
set_scan_configuration -style multiplexed_flip_flop
set_scan_configuration -clock_mixing no_mix
set_scan_configuration -internal_clocks single
set_dft_signal -view spec -type scanenable -active 1 -port SCAN_ENA
set_dft_signal -view spec -type testmode -active 1 -port SCAN_TEST
set_dft_signal -view existing_dft -type TestMode -port SCAN_TEST  -active_state 1
set_dft_signal -view existing_dft -type Reset    -port reset    -active_state 0
set_dft_signal -view existing_dft -type ScanClock -port SCAN_CLK -timing {45 55}
set_dft_signal -view existing_dft -type ScanEnable  -port SCAN_ENA -active_state 1
set_dft_signal -view spec       -type ScanDataIn  -port PIN_SI
set_dft_signal -view spec       -type ScanDataOut -port PIN_SO
set_scan_configuration -chain_count 1
set_scan_path -view spec c0 -scan_data_in PIN_SI -scan_data_out PIN_SO

#set_autofix_configuration -type clock -control_signal SCAN_TEST -test_data PIN_SI
#set_autofix_configuration -type reset -control_signal SCAN_TEST -test_data PIN_SO
#compile -scan

create_test_protocol
# -capture_procedure multi_clock
preview_dft
insert_dft
report_constraint -all_violators
report_scan_path
dft_drc -verbose -coverage_estimate
write_test_protocol -output dfttest.spf
#*********************** * end insert scan  *****************************
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
# Uniquify
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
uniquify

#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
# Pass0 compile
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
compile_ultra

#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
# Report timing & area
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
report_cons -all_vio
report_timing -max 100
report_area
report_area -hierarchy

#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
# Write out netlist
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
change_names -rules verilog -hier
write -f verilog -hier -o $design_top.vn
write -f ddc -hier -o $design_top.ddc