Design of High-Voltage-Tolerant ESD Protection in Low-Voltage CMOS Processes

semico_ljj

Design of High-Voltage-Tolerant ESD Protection
Circuit in Low-Voltage CMOS Processes

Ming-Dou Ker, Fellow, IEEE, and Chang-Tzu Wang, Student Member, 3 IEEE

Abstract—Two new electrostatic discharge (ESD) protection
5 design by using only 1 × VDD low-voltage devices for mixed6
voltage I/O buffer with 3 × VDD input tolerance are proposed.
7 Two different special high-voltage-tolerant ESD detection circuits
8 are designed with substrate-triggered technique to improve ESD
9 protection efficiency of ESD clamp device. These two ESD de10
tection circuits with different design concepts both have effective
11 driving capability to trigger the ESD clamp device on. These ESD
12 protection designs have been successfully verified in two different
13 0.13-μm 1.2-V CMOS processes to provide excellent on-chip ESD
14 protection for 1.2-V/3.3-V mixed-voltage I/O buffers.
15 Index Terms—Electrostatic discharge (ESD), low-voltage
16 CMOS, mixed-voltage I/O, substrate-triggered technique.

[ 本帖最后由 semico_ljj 于 2008-12-14 18:58 编辑 ]

semico_ljj

Ming-Dou Ker, Fellow, IEEE, and Chang-Tzu Wang, Student Member, 3 IEEE

semico_ljj

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 9, NO. 1, MARCH 2008

monkeygoku

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keqihu

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bdkqh

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raydcj

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raydcj

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suxiaoxin

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