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It's basic DC. Doc.
content as following:
INTRODUCTION........................
BASIC SYNTHESIS FLOW................
CORRECT INPUT FILES.................
DEFINING LIBRARIES..................
SYNOPSYS SETUP FILE.................
Setup File Description..............
EFFICIENTLY READING FILES...........
ANALYZE / ELABORATE VERSUS READ_FILE
analyze.............................
Elaborate...........................
link Command........................
read_file...........................
Comparison..........................
PRESTO ON VERSUS PRESTO OFF.........
Presto Variables....................
READ EXAMPLE........................
hdlin_report_inferred_modules.......
Generic Components..................
FOCUSED CONSTRAINTS.................
DESIGN ENVIRONMENT..................
Operating Conditions................
Wire Load Models....................
Wire Load Model Example.............
System Interface....................
CONSTRAINTS.........................
Timing..............................
Area................................
Design Rules........................
UNUSUAL CLOCK CONSTRAINTS...........
CONCLUSION.......................... |
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