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发表于 2008-5-5 14:14:38
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good model card!
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* CZ6H SPICE MODEL *
* FOR NORMAL TR.S, NATIVE TR.S, PNP BJTS *
* fd type nmos and resistance *
* 2003/07/03 *
* VER. 2.0 *
* SHANGHAI HUAHONG-NEC *
****************************************************
*
*******************************************************
* CZ6H TR./PNP BJT MODEL *
* TR. PARAMETER FOR HSPICE LEVEL53 (BSIM3V3.2) *
* BJT PARAMETER FOR HSPICE LEVEL1 *
* NOTE:USE THIS MODEL WITH HSPICE VERSION 2000.4 *
* 99.4 *
* DO NOT USE WITH THE OTHER VERSIONS *
* << HHNEC CONFIDENTIAL AND PROPRIETARY >> *
*******************************************************
*
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* IN THIS MODEL LIB CONTAINS: *
* 1. LIB TT *
* SS *
* FF *
* SF *
* FS *
* ( NORMAL DEVICE CORNER MODELS) *
* *
* 2. LIB TT_NA *
* SS_NA *
* FF_NA *
* ( NATIVE DEVICE CORNER MODELS) *
* *
* 3. LIB TT_FD *
* SS_FD *
* FF_FD *
* SF_FD *
* FS_FD *
* ( FD TYPE NMOS CORNER MODELS) *
* *
* 4. LIB BIP *
* ( P+/NW/PSUB VERTICAL PNP BIPLOAR) *
* *
* 5. LIB RES *
* ( RESISTOR MODEL) *
********************************************************
*
********************************************************
* *
* IN THIS MODEL FILE, FOUR MOS MODELS, ONE *
* BIPOLAR MODELS ARE SUPPLIED. THEY ARE: *
* *
* *
* 1. NENH -- FOR NORMAL NMOS *
* 2. PENH -- FOR NORMAL PMOS *
* 3. NNON -- FOR NATIVE NMOS *
* 4. N_FD -- FOR FD BUFFER NMOS *
* 5. PNP5 -- FOR BIPOLAR PNP4.8_13 *
* *
********************************************************
* subckt name are list below: *
* *
* Device Name subckt name: *
* -------------------------------------------------- *
* FD Type NMOS: *
* FD Tr. nch_fd *
* *
* Resistance: *
* N-well rnwell *
* N+diffusion rndiff *
* P+diffusion rpdiff *
* polycide rplcd *
* metal1 rme1 *
* metal2 rme2 *
* metal3 rme3 *
* metal4 rme4 *
* Rpoly rrpoly *
********************************************************
*
1. CZ6H Normal MOS spice model
1.1 CZ6H target spec. (Tj=27C)
Ln=Lp=0.54+/-0.04um
Vtn=0.65V+/-0.1V Vtp=-0.8V+/-0.15V
Ionn/Ionp=4.3mA/-2.2mA(Typical case)
Tox=155+/-10A
@Vt equals to Vgs for VDS=+/-5.0V, IDS=+/-1uA, W=50um.
@Ion equals to IDS/5 for VDS=VGS=+/-5.0V, W=50um.
1.2 Model name
nch model name = NENH
pch model name = PENH
1.3 Model spec.
(1)Typical case LIB: TT
+Ln=0um Ionn= 4.3mA Vtn= 0.65V Tox=155A
+Lp=0um Ionp=-2.2mA Vtp=-0.80V Tox=155A
(2)Fast case LIB: FF
+Ln=-0.04um Ionn= 4.68mA Vtn= 0.55V Tox=145A
+Lp=-0.04um Ionp=-2.55mA Vtp=-0.65V Tox=145A
(3)Slow case LIB: SS
+Ln=+0.04um Ionn= 3.93mA Vtn= 0.75V Tox=165A
+Lp=+0.04um Ionp=-1.87mA Vtp=-0.95V Tox=165A
(4)VtN Low - VtP High case LIB: FS
+Ln=0um Ionn= 4.48mA Vtn= 0.55V Tox=155A
+Lp=0um Ionp=-2.04mA Vtp=-0.95V Tox=155A
(5)VtN High - VtP Low case LIB: SF
+Ln=0um Ionn= 4.11mA Vtn= 0.75V Tox=155A
+Lp=0um Ionp=-2.36mA Vtp=-0.65V Tox=155A
1.4
Perimeter of the drain and source junctions including the channel edge
shuld be always assigned by PD and PS in the netlist as shown below.
PD=2W+2D
Poly
+--+
| |
A +----------+ +----------+
| | | | |
| | | | |
W| | drain | | source |
| | | | |
| | | | |Diff
v +----------+ +----------+
<--------->| |
D ~ ~
1.5
Area of the drain and source junctions shuld be always assigned
by AD and AS in the net list as shown below.
AD=W*D
1.6 Minimum gate length in net list and in design rule should be assigned
Ln=Lp=0.54um.
Lminn=Lminp=0.54um is in net list and in design rule.
Lminn=Lminp=0.54um is on wafer.
2. CZ6H NATIVE NMOS SPICE MODEL
2.1 CZ6H Native Device target spec. (Tj=27C)
L = 2.4+/-0.04um Ion= 3.36mA Vt= -0.22+/-0.05V
Tox= 155+/-10A
@Ion equals to IDS/5 for VDS=VGS=5V, W=50um.
@Vt equals to Vgs for VDS=5V, IDS=1uA, W=50um.
2.2 Model name
model name = nnon
2.3 Model spec.
(1)Typical case
LIB name: TT_NA
L+=0.00um W+=0.00um Tox+=0A Vt+=0V Ion=3.36mA
(2)Fast case
LIB name: FF_NA
L+=-0.04um W+=+0.12um Tox+=-10A Vt+=-0.05V
(3)Slow case
LIB name: SS_NA
L+=+0.04um W+=-0.12um Tox+=+10A Vt+=+0.05V
2.4
Perimeter of the drain and source junctions including the channel edge
should be always assigned by PD and PS in the net list as shown below.
PD=2W+2D
____Poly
| |
___________| |___________
| | | |
| | | |
| | | |
W | drain | | source |
| | | |
|___________| |___________|Diff
D | |
| |
~ ~
2.5
Area of the drain and source junctions should be always assigned
by AD and AS in the net list as shown below.
AD=W*D
3. PNP Parasitic BJT
The model parameters are extracted based on the pattern which
emitter(P+) area is 4.8*4.8um2 and Base(Nwell) area is 9.12*9.12um2.
3.1 LIB and Model Name:
LIB: BIP
MODEL: PNP5
3.2 Model usage:
Temperature range: -40~125
This model only applies to the PNP device with fixed size shown above.
This model only applies to the PNP device on CZ6 series Processes.
4. CZ6H FD TYPE NMOS SPICE MODEL
4.1.CZ6H FD TYPE NMOS target spec. (Tj=23C)
Ln=0.81+/-0.04um Tox=155+/-10A
4.2.Model name : none
(Please use the subckt : nch_fd)
4.3.Subckt name : nch_fd
sample :
.LIB TT_FD
x1 drain gate source sub nch_fd
+wn=50u adn='2.46u*(wn+1.02u*2) pdn='2.46u*2+(wn+1.02u*2)'
+asn='1.83u*wn' psn='1.83u*2+wn*2'
The wn is channel width of FD buffer.
The adn is nwell area in drain of FD buffer.
The pdn is nwell perimeter in drain of FD buffer.
The asn is Diffusion area in source of FD buffer.
The psn is diffusion perimeter in source of FD buffer.
4.4.Model spec.
(1)Typical case
LIB name: TT_FD
Ln=0.81um, delta L= 0.00um, delta Vt= 0.0V, Tox=155A
(2)Fast case
LIB name: FF_FD
Ln=0.81um, delta L=-0.04um, delta Vt=-0.1V, Tox=145A
(3)Slow case
LIB name: SS_FD
Ln=0.81um, delta L= 0.04um, delta Vt= 0.1V, Tox=165A
(4)Nch Low - Pch High case
LIB name: FS_FD
Ln=0.81um, delta L= 0.00um, delta Vt=-0.1V, Tox=155A
(5)Nch High - Pch Low case
LIB name: SF_FD
Ln=0.81um, delta L= 0.00um, delta Vt= 0.1V, Tox=155A
5. Resistor Model usage:
Please use subckt |
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