model PLL in PrimeTime

kevinwjs

Modeling the behavior of  PLLs in PrimeTime

hang1

sherryshao

这么好的东西，太感谢了

sherryshao

请问楼主，这是专门针对PLL的PT constraint吗？

kevinwjs

This paper discusses basic modeling techniques for PLLs, duty cycle modeling, jitter and skew, and on-chip-variation effects.

1 Introduction........................................................................................................................3
2 The basic insertion delay cancellation (idc) PLL................................................................... 4
2.1 The problem – too muchdelay......................................................................................................................4
2.2 The solution – the insertion delay cancellationPLL......................................................................................5
2.3 Timing the basic idc PLL in PrimeTime.......................................................................................................6
2.4 The IDC multiplier PLL.............................................................................................................................15
2.5 The PLL model itself.................................................................................................................................24
2.6 Performance considerations........................................................................................................................25
3 Duty Cycle........................................................................................................................26
3.1 Internal clocks (other thanPLLs)................................................................................................................26
3.2 Primary input clocks and PLLs...................................................................................................................28
3.3 Applying this to our multiplier pllcircuit....................................................................................................35
3.4 When to use thesetechniques.....................................................................................................................41
4Jitter.................................................................................................................................42
4.1 Jitter, skew, anduncertainty.......................................................................................................................42
4.2 My definition ofjitter.................................................................................................................................42
4.3 Sources ofjitter..........................................................................................................................................43
4.4 Effects of jitter on different sorts ofpaths....................................................................................................43
4.5 Modeling jitter withset_clock_uncertainty..................................................................................................47
4.6 Applying jitter specs to the example circuit – simple case...........................................................................47
4.7 Generatedclocks........................................................................................................................................54
4.8 What about fallingedges?..........................................................................................................................56
4.9 Applying jitter specs to the example circuit – complex case........................................................................57
5 On-chipVariation..............................................................................................................64
5.1 The classic OCV case................................................................................................................................64
5.2 EnterCRPR...............................................................................................................................................67
5.3 OCV and PLLs..........................................................................................................................................69
5.4 The OCV/PLL excess pessimismproblem...................................................................................................75
6 OCV/PLL excess pessimism workarounds......................................................................... 79
6.1 Forcing OCV off on the fbpath...................................................................................................................79
6.2 Referencing the i/os to the feedbackclock...................................................................................................96
6.3 The shell game........................................................................................................................................105
7Conclusion.....................................................................................................................111
8 Acknowledgements ......................................................................................................... 112
9 References......................................................................................................................113
10Appendix.....................................................................................................................114
10.1 The PLL model itself..............................................................................................................................114

dura

goood

zk555

感謝分享
正好在學dc

147107186s

dddddddddddddddddd

0xffff

好东西
谢谢楼主

opqfeixue

谢谢了！！！