【瑞典皇家工学院】【PHD】【 PLL Frequency Synthesizers】

tianxian · 发表于 2009-3-31 00:08:08

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Abstract

Thanks to its ability to generate a stable yet programmable output frequency, Phase Locked
Loop (PLL) frequency synthesizers are found in most modern radio transceivers. All practical
PLL implementations suffer from unwanted frequency components such as phasenoise
and spurious tones, and since these components affect system performance they
must be predicted and minimized.
This thesis discuss the design and implementation of fully integrated PLL circuits. Techniques
to predict system performance are investigated. The strongly non-linear operation
of PLL building blocks are analyzed, using both analytical and numerical methods.
Techniques to reduce impact of interferer down-conversion and noise folding are suggested.
Methods to perform automatic calibration in order to make circuits less sensitive
to process variations are proposed. The techniques are verified through a number of PLL
implementations.
The design and implementation of a transceiver targeting a dual band IEEE 802.11 a/b/g
wireless LAN operation is discussed. The circuit use two PLL:s operating at 1310 to 1510
MHz and 3.84 GHz respectively. Noise contributions of various PLL building blocks and
their impact on over all system performance are analyzed. The combined integrated phase
noise is below -34 dBc, and measured transceiver Error Vector Magnitude (EVM) is better
than 2.5 dB in both the 2.4 and 5 GHz bands.
A low power frequency synthesizer targeting Frequency Shift Keying applications such
as ZigBee and BlueTooth is presented. The synthesizer use open-loop direct modulation
of the carrier, but unlike conventional implementations, the proposed synthesizer is open
both when transmitting and receiving data. This allows the use of a small area on-chip
loop filter without violating noise or spurious requirements. To handle the frequency
drift normally associated with open-loop implementations, a low-leakage charge-pump is
proposed. The synthesizer is implemented using a 0.18μm CMOS process. Total power
consumption is 9 mW and the circuit area including the VCO inductors and on-chip loopfilter
is 0.32mm2. Measured leakage current is less than 2 fA.
A small area amplitude detector circuit is proposed. The wide-band operation and small
input capacitance make the circuit suitable for embedding in an RF system on-chip, allowing
measurement of on-chip signal levels and automatic calibration.

Finally an oscillator topology reducing the phase noise in voltage controlled oscillators
is suggested. By using on-chip decoupling and an amplitude control circuit to adjust
oscillator bias, the impact of current source noise is eliminated. The theoretical phase
noise is reduced 3.9 dB compared to a conventional LC oscillator using the same bias
current.

Contents
Abstract iii
Acknowledgments v
List of appended papers xi
Related work not included xiii
Summary of appended papers xv
1 Introduction 1
1.1 PLL operation principle . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Transceiver overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 PLL performance parameters 13
2.1 Frequency range and accuracy . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 Settling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 Spurious tones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4 Phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.5 Phase noise impact on system performance . . . . . . . . . . . . . . . . 25
2.6 Phase noise in OFDM system . . . . . . . . . . . . . . . . . . . . . . . . 27
2.7 Amplitude and phase matching . . . . . . . . . . . . . . . . . . . . . . . 32
2.8 Other PLL design considerations . . . . . . . . . . . . . . . . . . . . . . 33

3 PLL modeling and simulation 37
3.1 PLL type and order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2 Linear models of PLL building blocks . . . . . . . . . . . . . . . . . . . 40
3.3 Linear PLL model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.4 Discrete time PLL model . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.5 Numerical PLL models . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.6 Mixed-signal PLL model . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.7 Simulating PLL performance . . . . . . . . . . . . . . . . . . . . . . . . 54
4 PLL noise analysis 59
4.1 Noise in digital circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2 Phase Frequency Detector . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.3 Folding of noise and interferers in Charge-Pump . . . . . . . . . . . . . . 64
4.4 Oscillator phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.5 Reference oscillator noise . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.6 Noise in DS noise shaper . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.7 Linear PLL noise model . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.8 Simulating PLL noise using circuit simulator . . . . . . . . . . . . . . . 76
4.9 Discrete time and numerical noise simulation . . . . . . . . . . . . . . . 80
4.10 PLL noise optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5 Oscillators 89
5.1 Oscillator principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.2 CMOS LC-VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.3 Pulse wave LC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.4 Comparison LC and pulse wave VCO . . . . . . . . . . . . . . . . . . . 118
6 Conclusion 121
References 123
A Calculation of loop-filter components 133
A.1 Calculation of frequency of pole and zero . . . . . . . . . . . . . . . . . 135
A.2 Calculation of component values . . . . . . . . . . . . . . . . . . . . . . 136
B Behavioral models 139
B.1 VCO behavioral model . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
B.2 Divider behavioral model . . . . . . . . . . . . . . . . . . . . . . . . . . 140