ISE 扩频？

sohik

这是我们的一个课程作业，我不学这个方向，马上要交了。。。但是IP核都没更新完，希望大神能给解释下这部分代码啊。这个是程序的链接。希望能有大神给看下http://pan.baidu.com/s/1i36ad3Ralways @(posedge clk)
begin
if (en == 1 && en_ram_send)
  begin
    if(dspdatacon == 1)

   begin

  if(send_counter[19:13]<96 && send_frame_once == 0)

     begin

    addr[6:0] <= send_counter[19:13];

frame_head <= 1;

  end

  else

  begin

frame_head <= 0;

send_frame_once <= 1;//已发送

  end

end

    else if(clr || ((dspdatacon || frame_data_96)==0))

       send_frame_once <= 0;

  end

begin

end
end
always @(posedge clk)
begin
if(clr || ((dspdatacon || frame_data_96)==0))

begin

send_counter <= 0;

end
else if (en == 1)

begin

pn_adr <= send_counter[12:3];

if(dspdatacon == 1)

   wea <= 1;

else

   wea <= 0;

if(send_counter[2:0] == 3'b111)

en_8 <= 1;

else

en_8 <= 0;

if(send_counter[12:0] == 13'b0111111110111)

clk_wuma <= ~clk_wuma;//信号翻转

if(send_counter[12:0] == 13'b1111111110111)

begin


clk_wuma <= ~clk_wuma;

en_127_8 <= 1;

send_counter[12:0] <= 0;

send_counter[19:13] <= send_counter[19:13] + 1;

clk_wuma <= ~clk_wuma;

   if(frame_head == 0 && frame_data_96 == 1)

    begin

  addrb_data_read <= addrb_data_read + 1;

  end


   else

  addrb_data_read <= 0;
if(dspdatacon == 1)

  begin

    frame_data_96 <= 1;

addr_write <= addr_write + 1 ;

wait_once <= 1'b0;

counter_wait_96<= 0;

  end


   else begin

   
  addr_write <= 0 ;

  if(counter_wait_96 < 96 && wait_once ==0 && frame_data_96==1)

    counter_wait_96 <= counter_wait_96 + 1;

  else begin

counter_wait_96 <= 0;

wait_once <= 1;

frame_data_96 <= 0;

        end

      end

       end

    else

  begin

send_counter[12:0] <= send_counter[12:0] + 1;

en_127_8 <= 0;

  end

end

else begin

en_8 <= 0;

en_127_8 <= 0;

end
end

always @(posedge clk)
begin

if(clr) begin

  rcosflt_in <= 0;

end

else if(en_8 == 1)begin

  begin

      if((dspdatacon || frame_data_96) == 1)

begin

spectrum_data_out <= inp_dif ^ pncode;

case (spectrum_data_out)

      
1'b0  : begin

                  rcosflt_in <=2'b01;

               end

     
1'b1  : begin

                  rcosflt_in <= 2'b11;

               end


   
endcase

end

else

rcosflt_in <= 2'b00;

  end

end

end
always @(posedge clk)
begin

if(clr) begin

inp_dif <= 0;

end

else if(en_127_8 == 1)begin

      if(frame_head ==1 )

begin

  inp_dif <= send_framehead ^ inp_dif;

end

      else

begin

     inp_dif <= data_ram_out ^ inp_dif;

end

out_impulse_inp <= impulse_inp;

end
end
endmodule

killyliu

没人看得懂你这个

sohik

回复 2# killyliu


   额。不好意思，这一块很多，我不知道应该怎么附。。。

killyliu

你没有前后文，呵呵呵。。。。。。。。。。