本帖最后由 小干爹z2z 于 2013-12-10 09:25 编辑
回复 6# 729050850 Threshold Scaling
Example: driver delay threshold: 50% load delay threshold : 25% transition time 0% - 100% (ideal ramp) : 1.00ns net delay : 0.10ns driver pin: delay threshold of 50% VDD is reached after 0.5 ns load pin : delay threshold of 30% VDD is reached after 0.1ns (net delay) + 0.25ns = 0.35ns reported net delay : 0.35ns - 0.5ns = -0.15nsWith a short net and a long transition time, the 25% threshold at the load pin is reached earlier than the 50% threshold at the driver pin. The measured delay time between 25% and 50% is negative.
Voltage Scaling
driver delay threshold: 50% driver supply voltage : 3.0V => absolute threshold : 1.50V load delay threshold : 50% load supply voltage : 1.5V => absolute threshold : 0.75V transition time 0% - 100% of 3.0V (ideal ramp) : 1.00ns ramp starting at 0ns at driver pin driver pin: delay threshold of 1.50V is reached after 0.50ns net delay : 0.10ns load pin : 1.50V is reached after 0.50ns + 0.10ns = 0.60ns => delay threshold of 0.75V is reached after 0.25ns + 0.10ns = 0.35ns reported net delay : 0.35ns - 0.50ns = -0.15nsCrosstalk Delay Effects Point DTrans Trans Delta Incr Path ----------------------------------------------------------------------------- inst_top/u2661/Z (ND4) 0.08 0.20 & 2.60 r inst_top/u2662/B (OR2) 0.00 0.08 -0.10 -0.08 & 2.52 r Stage delay (cell + net): 0.20 - 0.08 = 0.12Derating set_timing_derate -early 0.75 net delay (without crosstalk): 0.200ns stage delta delay: -0.184ns2003.12: (0.200ns - 0.184ns) * 0.75 = 0.012ns2004.06: (0.200ns * 0.75) + (-0.184ns * 1.25) = -0.08ns
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发表于 2013-12-8 10:00:39
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发表于 2013-12-10 22:11:35
