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Job Description and Responsibility:
- Participate SoC level DFT architecture definition
- Implement DFT design for the SoC chips, cooperating with design team
- Develop the high coverage and cost effective test patterns.
- Generate and verify DFT patterns.
- Evaluate and establish advanced DFT tools and flow.
- Support other teams for DFT related problems
Requirement:
- BSEE required and MSEE preferred.
- Minimum 2+ years of DFT or related design experience
- Good knowledge of IC design flow, including coding, simulation, verification, synthesis and STA.
- Be skilled in the main EDA tools for design and simulation such as ncsim, RC/DC, Formality/LEC and PT.
- Be familiar with Synopsys/Mentor DFT flow and tools
- Proficient in Verilog/VHDL language.
- Be familiar with shell/TCL/Perl grogram.
- Good English communication skills
- Self-motivated and good team player
KT Human Resources Consulting Company (Shanghai) was established in 2001 in response to a need for a recruitment consultancy to be an active, contributing member of the semiconductor community, as opposed to simply a supplier to it.We provide professional search and talent acquisition in the Integrated Circuit、Electronic、Telecommunications industry of international corporations in Greater China. Our client list contains numerous international companies, many of them are long-term customers.
If you interested in the job, pls sent your cv to: hr@kthr.com, thanks! |
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