请问Veriolg中1和1'b1有什么不同？？

ineedpower

我在写Verilog的时候，刚开始使用下面语句
reg [3:0] wrptr,rdptr;

if(wrptr+1 == rdptr)
   begin
         .....
  end
仿真错误，

改成如下语句
if(wrptr+1'b1 == rdptr)
   begin
         .....
  end
仿真就正确了，请问为什么呢 1和1'b1有什么不同呢，在if语句中。
我知道如果是计数器
counter<=counter+1;
counter<=counter+1'b1;
这两个是相同的吧~~

谢谢

humann

I think it is a bug of your simulator. Which tool do you use? I tried the following code in vcs and found no error.


// filename: one.v
// vcs -o one one.v
module one;
   reg [3:0] wrptr,rdptr;

   initial
     if(wrptr+1 == rdptr)
       begin
      $display("ok");      
       end
   
endmodule

ineedpower

thanks

the tool is modelsim 6.1f

i found that many verison of modelsim have different kinds of bug, sucks!!

humann

you are welcome.

It is hard to call this behavior a bug, because it isn't specified by IEEE. The EDA company has full freedom to implement it. But in order to keep you code portable between different tools, try to  code as accurately as possible. It can save you several hours later.

By the way, vcs has a lot of bugs too.

ineedpower

   

原帖由 humann 于 2009-2-24 17:43 发表

                               
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It is hard to call this behavior a bug, because it isn't specified by IEEE. The EDA company has full freedom to implement it. But in order to keep you code portable between differe ...

yeah, it took me almost half a day to debug this.

thanks again  ,good luck to you ~~~~~

yuanpin318

1'b1 is better, no other defination.

If 1, diff simulator can have diff explanation.

ineedpower

thanks~~~

xudeqiang

1 means 32'b00000000000000000000000000000001 , it is different from 1'b1;
when you user rptr + 1 the result will be 32 bit wide it maybe different from wptr.

humann

   

原帖由 xudeqiang 于 2009-2-25 13:39 发表

                               
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1 means 32'b00000000000000000000000000000001 , it is different from 1'b1;
when you user rptr + 1 the result will be 32 bit wide it maybe different from wptr.

You are right.

Verilog is a weak-typed language. It is the most important difference between verilog and vhdl. The compiler do some type conversion silently, It allows a program in verilog "easy" to write and  hard to debug.

zhouhong

I think this mistake can caused by two reasons . One is just the debug of simulator tools, the other just the 1 is 32-bit wide,in contrast, 1'b1 is just the one-bit.