library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity led_water is
port(
clk : in std_logic;
output : out std_logic_vector(3 downto 0));
end led_water;
architecture arch_ledwater of led_water is
signal counter : std_logic_vector(25 downto 0);
signal buff : std_logic_vector(1 downto 0);
begin
process(clk,buff)
begin
if clk'event and clk = '1' then
counter <= counter+1;
end if;
if counter = "10111110101111000010000000" then
buff <= buff+1;
counter <= "00000000000000000000000000";
end if;
case buff is
when "00" => output <= "1110";
when "01" => output <= "1101";
when "10" => output <= "1011";
when "11" => output <= "0111";
when others => NULL;
end case;
end process;
end arch_ledwater;