|
|
楼主 |
发表于 2015-9-8 20:18:35
|
显示全部楼层
回复 32# joeyshen
SPARC processor, known an M7. This chip will have 32 S4 SPARC cores (each with up to eight dynamic threads), 64MB of L3 cache, eight DDR4 memory controllers (up to 2TB per processor and 160GBps of memory bandwidth with DDR4-2133) and eight data analytics accelerators connected over an on-chip network.
The chip is organized into eight clusters with four cores each with shared L2 cache and a partitioned 8MB of L3 cache with more than 192GBps bandwidth between a core cluster and its local L3 cache. In comparison to the M6 (a 28nm chip with 12 3.6GHz SPARC S3 cores), the M7 delivers 3-3.5 times better performance on memory bandwidth, integer throughput, OLTP, Java, ERP systems, and floating-point throughput. Stephen Phillips, Oracle's Senior Director of SPARC Architecture, said the goal was a step-function increase in performance, rather than incremental gains.The M7 can scale to 8 sockets glue-less (up to 256 cores, 2,000 threads, and 16TB of memory), and with an ASIC switch to manage traffic between them in an SMP configuration, up to 32 processors, so you could end up with a system with 1,024 cores, 8,192 threads, and up to 64TB of memory. Pretty impressive. Oracle said it offers 3 to 3.5 times better performance on a variety of tests, compared with last year's SPARC M6. The company said this will be optimized for Oracle's own software stack, manufactured on a 20nm process, and available in systems sometime next yea
|
|
/2 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2015-9-8 17:57:17
