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我写了一个简单的小代码来实验自定义IP核的读写
开发环境: Quartus 12.0 & Qsys & Nios II 12.0 Software Build Tools for Eclipse
Verilog 代码如下:
module LED_module
(
input CLK,
input nRST,
input read,
input write,
input address,
output [31:0]readdata,
input [31:0]writedata,
input [3:0]byteenable,
input chipselect,
output [3:0]LED_out
);
//Write data
reg [31:0]rLED1;
reg [31:0]Enable;
always @ ( posedge CLK or negedge nRST )
if( !nRST )
begin
rLED1 <= 32'd1;
Enable <= 32'd1;
end
else if( write & chipselect & !address )
begin
if( byteenable[0] ) rLED1[7:0] <= writedata[7:0];
if( byteenable[1] ) rLED1[15:8] <= writedata[15:8];
if( byteenable[2] ) rLED1[23:16] <= writedata[23:16];
if( byteenable[3] ) rLED1[31:24] <= writedata[31:24];
end
else if( write & chipselect & address )
begin
if( byteenable[0] ) Enable[7:0] <= writedata[7:0];
if( byteenable[1] ) Enable[15:8] <= writedata[15:8];
if( byteenable[2] ) Enable[23:16] <= writedata[23:16];
if( byteenable[3] ) Enable[31:24] <= writedata[31:24];
end
//Read data
reg [31:0]rdata;
always @ (*)
if( !nRST ) rdata <= 32'd0;
else if( read & chipselect & !address ) rdata <= rLED1;
else if( read & chipselect & address ) rdata <= Enable;
else rdata <= 32'd0;
assign readdata = rdata;
assign LED_out = Enable[0] ? rLED1[3:0] : 4'd0;
endmodule
软件中自定义结构体
typedef struct {
volatile unsigned long int DATA0;
volatile unsigned long int ENABLE;
}LED_STR;
#define LED ((LED_STR *) LED_MODULE_0_BASE)
软件主程序如下:
int main(void)
{
unsigned long a,b;
a = LED->DATA0;
b = LED->ENABLE;
printf("LED = %ld\n",a);
printf("En = %ld\n",b);
while (1){
LED->DATA0++;
usleep(800000);
LED->ENABLE++;
usleep(800000);
}
return 0;
}
发生的问题就是
rLED1 (寄存器 偏移量为0) 读写都正常 printf为1
Enable(寄存器 偏移量为1) 无法读写 printf为-595508971
为何~~~~~ |
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