LDO 的 重要问题

sh_nouvell

回复 19# hszgl


    vds_sat might change accordingly with Vgs but Vds is supposed to be not as long as LDO still has sufficient gain

hezudao

回复 19# hszgl


    服了你了

fengchunyi_2011

回复 20# hszgl
    当EA的输出过高或者过低时，其增益会明显下降！你可以仿真一下EA的增益随其输出DC电压变化情况！是增益降低导致失调电压增加！

jiang_shuguo

回复 22# hezudao


    呵呵

hszgl

回复 23# fengchunyi_2011


   哦，这下我看懂了。我以为你说的是失调电压导致增益下降。。那就反了。。。

hszgl

回复 21# sh_nouvell


   不太理解，你能举个具体点的例子解释一下么？

sh_nouvell

回复 26# hszgl


    i would say this is the fundamental characteristic of MOS device...you can find explanation in the 1st chapter of any IC design book...

hszgl

回复 27# sh_nouvell


    你说VGS变化的时候VDS可能不变我懂，但是我不理解的是在LDO的反馈回路里，怎么会出现pass transistor的VGS变化的情况呢？

sh_nouvell

回复 28# hszgl


    In an LDO, the operation region of the pass transistor might be varying according to the loading , which is equivantly to say Vgs is varying. Yet Vds is not necessarily changed because it is regulated by the high gain loop. Thats why i said as long as the loop gain is still high enough, Vds could be the same.

thewolftotem

top的人还是挺耐心的，楼上说的很清楚了。
pmos可看成可变电阻，vgs是它的控制电压，因为反馈环路，vgs随外部条件变化而变化，使得drain电压保持在额定值。