ADPLL 论文合集

happygrass

最近做了一个ADPLL的项目，收集了一些ADPLL的学习资料，和大家分享一下：

ROBERT BOGDAN STASZEWSKI的书：
All-Digital Frequency Synthesizer in Deep-Submicron CMOS

MIT博士论文：
Noise Shaping Techniques for Analog and Time to Digital Converters Using Voltage Controlled Oscillators

JSSC:
A 1 GHz ADPLLWith a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 um CMOS
A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology
A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques
A Digitally Controlled Oscillator in a 90 nm Digital CMOS Process for Mobile Phones
A PVT Tolerant 10 to 500 MHz All-Digital Phase-Locked Loop With Coupled TDC and DCO
Software Assisted Digital RF Processor (DRP™) for Single-Chip GSM Radio in 90 nm CMOS
A 2.4-GHz Low-Power All-Digital Phase-Locked Loop
Two-Dimensions Vernier Time-to-Digital Converter
An Embedded All-Digital Circuit to Measure PLL Response
A 86 MHz–12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS
A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation
A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter
Capacitive Degeneration in LC-Tank Oscillator for DCO Fine-Frequency Tuning
A 0.3–1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller
A Calibration-Free 800 MHz Fractional-N Digital PLL With Embedded TDC

TCAS:
An All-Digital Self-Calibration Method for a Vernier-Based Time-to-Digital Converter
Effect of Reference Clock Jitter and Demonstration of Near Image-Free Operation for the ADPLL
FPGA Vernier Digital-to-Time ConverterWith 1.58 ps Resolution and 59.3 Minutes Operation Range
Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL Observer-Controller Digital PLL
Analytical Expression of Quantization Noise in Time-to-Digital Converter Based on the Fourier Series Analysis
A Digital PLL Scheme for Three-Phase System Using Modified Synchronous Reference Frame
Recombination of Envelope and Phase Paths in Wideband Polar Transmitters
An FPGA-Based Linear All-Digital Phase-Locked Loop
A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm
Flicker Noise in Observer-Controller Digital PLL
Multimode Reconfigurable Digital ΣΔ Modulator Architecture for Fractional-N PLLs
Analysis and Design Techniques for Supply-Noise Mitigation in Phase-Locked Loops
All-Digital Frequency Synthesizer Using a Flying Adder
Software PLL Based on Random Sampling
Analysis of Harmonic Energy Distribution Portfolio for Digital-to-Frequency Converters

VLSI:
A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme

IETDL:
Fast-locking all-digital phase-locked loop with digitally controlled oscillator tuning word estimating and presetting

ELECTRONICS LETTERS:
Frequency synthesis using digital-to-frequency conversion and filtering

zain

好，顶一个

zeronet

nice. thanks.

nero007

haotiezi

rockycheng

Thank you very much!

calven

KANYIXIA

calven

KANYIXIA

nicist

很感谢楼主的分享

buildgates

很感谢楼主的分享

lisayoung

回复 1# happygrass


   谢谢！